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+#include <stddef.h>
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+#include <rtthread.h>
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+#include "addr2line.h"
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+
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+#define PROJECT_NAME "project"
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+#define addr2line_print rt_kprintf
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+
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+// 错误类型打印
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+#define DUMP_CPU_ARM_CORTEX_M0 0
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+#define DUMP_CPU_ARM_CORTEX_M3 1
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+#define DUMP_CPU_ARM_CORTEX_M4 2
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+#define DUMP_CPU_ARM_CORTEX_M7 3
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+
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+#define DUMP_CPU_PLATFORM_TYPE DUMP_CPU_ARM_CORTEX_M4
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+
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+/* system handler control and state register */
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+#ifndef DUMP_SYSHND_CTRL
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+ #define DUMP_SYSHND_CTRL (*(volatile unsigned int*) (0xE000ED24u))
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+#endif
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+
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+/* memory management fault status register */
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+#ifndef DUMP_NVIC_MFSR
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+ #define DUMP_NVIC_MFSR (*(volatile unsigned char*) (0xE000ED28u))
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+#endif
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+
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+/* bus fault status register */
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+#ifndef DUMP_NVIC_BFSR
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+ #define DUMP_NVIC_BFSR (*(volatile unsigned char*) (0xE000ED29u))
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+#endif
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+
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+/* usage fault status register */
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+#ifndef DUMP_NVIC_UFSR
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+ #define DUMP_NVIC_UFSR (*(volatile unsigned short*)(0xE000ED2Au))
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+#endif
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+
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+/* hard fault status register */
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+#ifndef DUMP_NVIC_HFSR
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+ #define DUMP_NVIC_HFSR (*(volatile unsigned int*) (0xE000ED2Cu))
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+#endif
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+
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+/* debug fault status register */
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+#ifndef DUMP_NVIC_DFSR
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+ #define DUMP_NVIC_DFSR (*(volatile unsigned short*)(0xE000ED30u))
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+#endif
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+
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+/* memory management fault address register */
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+#ifndef DUMP_NVIC_MMAR
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+ #define DUMP_NVIC_MMAR (*(volatile unsigned int*) (0xE000ED34u))
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+#endif
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+
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+/* bus fault manage address register */
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+#ifndef DUMP_NVIC_BFAR
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+ #define DUMP_NVIC_BFAR (*(volatile unsigned int*) (0xE000ED38u))
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+#endif
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+
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+/* auxiliary fault status register */
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+#ifndef DUMP_NVIC_AFSR
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+ #define DUMP_NVIC_AFSR (*(volatile unsigned short*)(0xE000ED3Cu))
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+#endif
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+
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+/**
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+ * Cortex-M fault registers
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+ */
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+struct dump_hard_fault_regs
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+{
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+ struct
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+ {
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+ unsigned int r0; // Register R0
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+ unsigned int r1; // Register R1
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+ unsigned int r2; // Register R2
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+ unsigned int r3; // Register R3
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+ unsigned int r12; // Register R12
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+ unsigned int lr; // Link register
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+ unsigned int pc; // Program counter
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+ union
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+ {
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+ unsigned int value;
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+ struct
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+ {
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+ unsigned int IPSR : 8; // Interrupt Program Status register (IPSR)
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+ unsigned int EPSR : 19; // Execution Program Status register (EPSR)
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+ unsigned int APSR : 5; // Application Program Status register (APSR)
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+ } bits;
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+ } psr; // Program status register.
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+ } saved;
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+
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+ union
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+ {
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+ unsigned int value;
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+ struct
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+ {
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+ unsigned int MEMFAULTACT : 1; // Read as 1 if memory management fault is active
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+ unsigned int BUSFAULTACT : 1; // Read as 1 if bus fault exception is active
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+ unsigned int UnusedBits1 : 1;
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+ unsigned int USGFAULTACT : 1; // Read as 1 if usage fault exception is active
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+ unsigned int UnusedBits2 : 3;
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+ unsigned int SVCALLACT : 1; // Read as 1 if SVC exception is active
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+ unsigned int MONITORACT : 1; // Read as 1 if debug monitor exception is active
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+ unsigned int UnusedBits3 : 1;
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+ unsigned int PENDSVACT : 1; // Read as 1 if PendSV exception is active
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+ unsigned int SYSTICKACT : 1; // Read as 1 if SYSTICK exception is active
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+ unsigned int USGFAULTPENDED : 1; // Usage fault pended; usage fault started but was replaced by a higher-priority exception
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+ unsigned int MEMFAULTPENDED : 1; // Memory management fault pended; memory management fault started but was replaced by a higher-priority exception
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+ unsigned int BUSFAULTPENDED : 1; // Bus fault pended; bus fault handler was started but was replaced by a higher-priority exception
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+ unsigned int SVCALLPENDED : 1; // SVC pended; SVC was started but was replaced by a higher-priority exception
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+ unsigned int MEMFAULTENA : 1; // Memory management fault handler enable
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+ unsigned int BUSFAULTENA : 1; // Bus fault handler enable
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+ unsigned int USGFAULTENA : 1; // Usage fault handler enable
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+ } bits;
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+ } syshndctrl; // System Handler Control and State Register (0xE000ED24)
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+
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+ union
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+ {
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+ unsigned char value;
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+ struct
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+ {
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+ unsigned char IACCVIOL : 1; // Instruction access violation
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+ unsigned char DACCVIOL : 1; // Data access violation
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+ unsigned char UnusedBits : 1;
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+ unsigned char MUNSTKERR : 1; // Unstacking error
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+ unsigned char MSTKERR : 1; // Stacking error
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+ unsigned char MLSPERR : 1; // Floating-point lazy state preservation (M4/M7)
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+ unsigned char UnusedBits2 : 1;
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+ unsigned char MMARVALID : 1; // Indicates the MMAR is valid
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+ } bits;
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+ } mfsr; // Memory Management Fault Status Register (0xE000ED28)
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+ unsigned int mmar; // Memory Management Fault Address Register (0xE000ED34)
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+
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+ union
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+ {
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+ unsigned char value;
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+ struct
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+ {
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+ unsigned char IBUSERR : 1; // Instruction access violation
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+ unsigned char PRECISERR : 1; // Precise data access violation
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+ unsigned char IMPREISERR : 1; // Imprecise data access violation
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+ unsigned char UNSTKERR : 1; // Unstacking error
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+ unsigned char STKERR : 1; // Stacking error
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+ unsigned char LSPERR : 1; // Floating-point lazy state preservation (M4/M7)
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+ unsigned char UnusedBits : 1;
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+ unsigned char BFARVALID : 1; // Indicates BFAR is valid
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+ } bits;
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+ } bfsr; // Bus Fault Status Register (0xE000ED29)
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+ unsigned int bfar; // Bus Fault Manage Address Register (0xE000ED38)
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+
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+ union
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+ {
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+ unsigned short value;
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+ struct
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+ {
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+ unsigned short UNDEFINSTR : 1; // Attempts to execute an undefined instruction
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+ unsigned short INVSTATE : 1; // Attempts to switch to an invalid state (e.g., ARM)
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+ unsigned short INVPC : 1; // Attempts to do an exception with a bad value in the EXC_RETURN number
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+ unsigned short NOCP : 1; // Attempts to execute a coprocessor instruction
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+ unsigned short UnusedBits : 4;
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+ unsigned short UNALIGNED : 1; // Indicates that an unaligned access fault has taken place
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+ unsigned short DIVBYZERO0 : 1; // Indicates a divide by zero has taken place (can be set only if DIV_0_TRP is set)
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+ } bits;
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+ } ufsr; // Usage Fault Status Register (0xE000ED2A)
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+
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+ union
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+ {
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+ unsigned int value;
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+ struct
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+ {
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+ unsigned int UnusedBits : 1;
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+ unsigned int VECTBL : 1; // Indicates hard fault is caused by failed vector fetch
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+ unsigned int UnusedBits2 : 28;
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+ unsigned int FORCED : 1; // Indicates hard fault is taken because of bus fault/memory management fault/usage fault
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+ unsigned int DEBUGEVT : 1; // Indicates hard fault is triggered by debug event
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+ } bits;
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+ } hfsr; // Hard Fault Status Register (0xE000ED2C)
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+
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+ union
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+ {
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+ unsigned int value;
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+ struct
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+ {
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+ unsigned int HALTED : 1; // Halt requested in NVIC
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+ unsigned int BKPT : 1; // BKPT instruction executed
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+ unsigned int DWTTRAP : 1; // DWT match occurred
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+ unsigned int VCATCH : 1; // Vector fetch occurred
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+ unsigned int EXTERNAL : 1; // EDBGRQ signal asserted
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+ } bits;
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+ } dfsr; // Debug Fault Status Register (0xE000ED30)
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+
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+ unsigned int afsr; // Auxiliary Fault Status Register (0xE000ED3C), Vendor controlled (optional)
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+};
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+
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+enum
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+{
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+ PRINT_MAIN_STACK_CFG_ERROR,
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+ PRINT_FIRMWARE_INFO,
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+ PRINT_ASSERT_ON_THREAD,
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+ PRINT_ASSERT_ON_HANDLER,
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+ PRINT_THREAD_STACK_INFO,
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+ PRINT_MAIN_STACK_INFO,
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+ PRINT_THREAD_STACK_OVERFLOW,
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+ PRINT_MAIN_STACK_OVERFLOW,
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+ PRINT_CALL_STACK_INFO,
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+ PRINT_CALL_STACK_ERR,
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+ PRINT_FAULT_ON_THREAD,
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+ PRINT_FAULT_ON_HANDLER,
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+ PRINT_REGS_TITLE,
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+ PRINT_HFSR_VECTBL,
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+ PRINT_MFSR_IACCVIOL,
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+ PRINT_MFSR_DACCVIOL,
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+ PRINT_MFSR_MUNSTKERR,
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+ PRINT_MFSR_MSTKERR,
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+ PRINT_MFSR_MLSPERR,
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+ PRINT_BFSR_IBUSERR,
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+ PRINT_BFSR_PRECISERR,
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+ PRINT_BFSR_IMPREISERR,
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+ PRINT_BFSR_UNSTKERR,
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+ PRINT_BFSR_STKERR,
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+ PRINT_BFSR_LSPERR,
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+ PRINT_UFSR_UNDEFINSTR,
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+ PRINT_UFSR_INVSTATE,
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+ PRINT_UFSR_INVPC,
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+ PRINT_UFSR_NOCP,
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+ PRINT_UFSR_UNALIGNED,
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+ PRINT_UFSR_DIVBYZERO0,
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+ PRINT_DFSR_HALTED,
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+ PRINT_DFSR_BKPT,
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+ PRINT_DFSR_DWTTRAP,
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+ PRINT_DFSR_VCATCH,
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+ PRINT_DFSR_EXTERNAL,
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+ PRINT_MMAR,
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+ PRINT_BFAR,
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+};
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+
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+static const char *const print_info[] = {
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+ [PRINT_MAIN_STACK_CFG_ERROR] = "ERROR: Unable to get the main stack information, please check the configuration of the main stack\n",
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+ [PRINT_FIRMWARE_INFO] = "Firmware name: %s, hardware version: %s, software version: %s\n",
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+ [PRINT_ASSERT_ON_THREAD] = "Assert on thread %s\n",
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+ [PRINT_ASSERT_ON_HANDLER] = "Assert on interrupt or bare metal(no OS) environment\n",
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+ [PRINT_THREAD_STACK_INFO] = "===== Thread stack information =====\n",
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+ [PRINT_MAIN_STACK_INFO] = "====== Main stack information ======\n",
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+ [PRINT_THREAD_STACK_OVERFLOW] = "Error: Thread stack(%08x) was overflow\n",
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+ [PRINT_MAIN_STACK_OVERFLOW] = "Error: Main stack(%08x) was overflow\n",
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+ [PRINT_CALL_STACK_INFO] = "Show more call stack info by run: addr2line -e %s%s -a -f %.*s\n",
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+ [PRINT_CALL_STACK_ERR] = "Dump call stack has an error\n",
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+ [PRINT_FAULT_ON_THREAD] = "Fault on thread %s\n",
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+ [PRINT_FAULT_ON_HANDLER] = "Fault on interrupt or bare metal(no OS) environment\n",
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+ [PRINT_REGS_TITLE] = "=================== Registers information ====================\n",
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+ [PRINT_HFSR_VECTBL] = "Hard fault is caused by failed vector fetch\n",
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+ [PRINT_MFSR_IACCVIOL] = "Memory management fault is caused by instruction access violation\n",
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+ [PRINT_MFSR_DACCVIOL] = "Memory management fault is caused by data access violation\n",
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+ [PRINT_MFSR_MUNSTKERR] = "Memory management fault is caused by unstacking error\n",
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+ [PRINT_MFSR_MSTKERR] = "Memory management fault is caused by stacking error\n",
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+ [PRINT_MFSR_MLSPERR] = "Memory management fault is caused by floating-point lazy state preservation\n",
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+ [PRINT_BFSR_IBUSERR] = "Bus fault is caused by instruction access violation\n",
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+ [PRINT_BFSR_PRECISERR] = "Bus fault is caused by precise data access violation\n",
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+ [PRINT_BFSR_IMPREISERR] = "Bus fault is caused by imprecise data access violation\n",
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+ [PRINT_BFSR_UNSTKERR] = "Bus fault is caused by unstacking error\n",
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+ [PRINT_BFSR_STKERR] = "Bus fault is caused by stacking error\n",
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+ [PRINT_BFSR_LSPERR] = "Bus fault is caused by floating-point lazy state preservation\n",
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+ [PRINT_UFSR_UNDEFINSTR] = "Usage fault is caused by attempts to execute an undefined instruction\n",
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+ [PRINT_UFSR_INVSTATE] = "Usage fault is caused by attempts to switch to an invalid state (e.g., ARM)\n",
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+ [PRINT_UFSR_INVPC] = "Usage fault is caused by attempts to do an exception with a bad value in the EXC_RETURN number\n",
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+ [PRINT_UFSR_NOCP] = "Usage fault is caused by attempts to execute a coprocessor instruction\n",
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+ [PRINT_UFSR_UNALIGNED] = "Usage fault is caused by indicates that an unaligned access fault has taken place\n",
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+ [PRINT_UFSR_DIVBYZERO0] = "Usage fault is caused by Indicates a divide by zero has taken place (can be set only if DIV_0_TRP is set)\n",
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+ [PRINT_DFSR_HALTED] = "Debug fault is caused by halt requested in NVIC\n",
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+ [PRINT_DFSR_BKPT] = "Debug fault is caused by BKPT instruction executed\n",
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+ [PRINT_DFSR_DWTTRAP] = "Debug fault is caused by DWT match occurred\n",
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+ [PRINT_DFSR_VCATCH] = "Debug fault is caused by Vector fetch occurred\n",
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+ [PRINT_DFSR_EXTERNAL] = "Debug fault is caused by EDBGRQ signal asserted\n",
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+ [PRINT_MMAR] = "The memory management fault occurred address is %08x\n",
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+ [PRINT_BFAR] = "The bus fault occurred address is %08x\n",
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+};
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+
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+static struct dump_hard_fault_regs regs;
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+
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275
|
+#if (DUMP_CPU_PLATFORM_TYPE != DUMP_CPU_ARM_CORTEX_M0)
|
|
|
276
|
+/**
|
|
|
277
|
+ * fault diagnosis then print cause of fault
|
|
|
278
|
+ */
|
|
|
279
|
+static void fault_diagnosis(void)
|
|
|
280
|
+{
|
|
|
281
|
+ if (regs.hfsr.bits.VECTBL)
|
|
|
282
|
+ {
|
|
|
283
|
+ addr2line_print(print_info[PRINT_HFSR_VECTBL]);
|
|
|
284
|
+ }
|
|
|
285
|
+ if (regs.hfsr.bits.FORCED)
|
|
|
286
|
+ {
|
|
|
287
|
+ /* Memory Management Fault */
|
|
|
288
|
+ if (regs.mfsr.value)
|
|
|
289
|
+ {
|
|
|
290
|
+ if (regs.mfsr.bits.IACCVIOL)
|
|
|
291
|
+ {
|
|
|
292
|
+ addr2line_print(print_info[PRINT_MFSR_IACCVIOL]);
|
|
|
293
|
+ }
|
|
|
294
|
+ if (regs.mfsr.bits.DACCVIOL)
|
|
|
295
|
+ {
|
|
|
296
|
+ addr2line_print(print_info[PRINT_MFSR_DACCVIOL]);
|
|
|
297
|
+ }
|
|
|
298
|
+ if (regs.mfsr.bits.MUNSTKERR)
|
|
|
299
|
+ {
|
|
|
300
|
+ addr2line_print(print_info[PRINT_MFSR_MUNSTKERR]);
|
|
|
301
|
+ }
|
|
|
302
|
+ if (regs.mfsr.bits.MSTKERR)
|
|
|
303
|
+ {
|
|
|
304
|
+ addr2line_print(print_info[PRINT_MFSR_MSTKERR]);
|
|
|
305
|
+ }
|
|
|
306
|
+
|
|
|
307
|
+#if (DUMP_CPU_PLATFORM_TYPE == DUMP_CPU_ARM_CORTEX_M4) || (DUMP_CPU_PLATFORM_TYPE == DUMP_CPU_ARM_CORTEX_M7)
|
|
|
308
|
+ if (regs.mfsr.bits.MLSPERR)
|
|
|
309
|
+ {
|
|
|
310
|
+ addr2line_print(print_info[PRINT_MFSR_MLSPERR]);
|
|
|
311
|
+ }
|
|
|
312
|
+#endif
|
|
|
313
|
+
|
|
|
314
|
+ if (regs.mfsr.bits.MMARVALID)
|
|
|
315
|
+ {
|
|
|
316
|
+ if (regs.mfsr.bits.IACCVIOL || regs.mfsr.bits.DACCVIOL)
|
|
|
317
|
+ {
|
|
|
318
|
+ addr2line_print(print_info[PRINT_MMAR], regs.mmar);
|
|
|
319
|
+ }
|
|
|
320
|
+ }
|
|
|
321
|
+ }
|
|
|
322
|
+ /* Bus Fault */
|
|
|
323
|
+ if (regs.bfsr.value)
|
|
|
324
|
+ {
|
|
|
325
|
+ if (regs.bfsr.bits.IBUSERR)
|
|
|
326
|
+ {
|
|
|
327
|
+ addr2line_print(print_info[PRINT_BFSR_IBUSERR]);
|
|
|
328
|
+ }
|
|
|
329
|
+ if (regs.bfsr.bits.PRECISERR)
|
|
|
330
|
+ {
|
|
|
331
|
+ addr2line_print(print_info[PRINT_BFSR_PRECISERR]);
|
|
|
332
|
+ }
|
|
|
333
|
+ if (regs.bfsr.bits.IMPREISERR)
|
|
|
334
|
+ {
|
|
|
335
|
+ addr2line_print(print_info[PRINT_BFSR_IMPREISERR]);
|
|
|
336
|
+ }
|
|
|
337
|
+ if (regs.bfsr.bits.UNSTKERR)
|
|
|
338
|
+ {
|
|
|
339
|
+ addr2line_print(print_info[PRINT_BFSR_UNSTKERR]);
|
|
|
340
|
+ }
|
|
|
341
|
+ if (regs.bfsr.bits.STKERR)
|
|
|
342
|
+ {
|
|
|
343
|
+ addr2line_print(print_info[PRINT_BFSR_STKERR]);
|
|
|
344
|
+ }
|
|
|
345
|
+
|
|
|
346
|
+#if (DUMP_CPU_PLATFORM_TYPE == DUMP_CPU_ARM_CORTEX_M4) || (DUMP_CPU_PLATFORM_TYPE == DUMP_CPU_ARM_CORTEX_M7)
|
|
|
347
|
+ if (regs.bfsr.bits.LSPERR)
|
|
|
348
|
+ {
|
|
|
349
|
+ addr2line_print(print_info[PRINT_BFSR_LSPERR]);
|
|
|
350
|
+ }
|
|
|
351
|
+#endif
|
|
|
352
|
+
|
|
|
353
|
+ if (regs.bfsr.bits.BFARVALID)
|
|
|
354
|
+ {
|
|
|
355
|
+ if (regs.bfsr.bits.PRECISERR)
|
|
|
356
|
+ {
|
|
|
357
|
+ addr2line_print(print_info[PRINT_BFAR], regs.bfar);
|
|
|
358
|
+ }
|
|
|
359
|
+ }
|
|
|
360
|
+
|
|
|
361
|
+ }
|
|
|
362
|
+ /* Usage Fault */
|
|
|
363
|
+ if (regs.ufsr.value)
|
|
|
364
|
+ {
|
|
|
365
|
+ if (regs.ufsr.bits.UNDEFINSTR)
|
|
|
366
|
+ {
|
|
|
367
|
+ addr2line_print(print_info[PRINT_UFSR_UNDEFINSTR]);
|
|
|
368
|
+ }
|
|
|
369
|
+ if (regs.ufsr.bits.INVSTATE)
|
|
|
370
|
+ {
|
|
|
371
|
+ addr2line_print(print_info[PRINT_UFSR_INVSTATE]);
|
|
|
372
|
+ }
|
|
|
373
|
+ if (regs.ufsr.bits.INVPC)
|
|
|
374
|
+ {
|
|
|
375
|
+ addr2line_print(print_info[PRINT_UFSR_INVPC]);
|
|
|
376
|
+ }
|
|
|
377
|
+ if (regs.ufsr.bits.NOCP)
|
|
|
378
|
+ {
|
|
|
379
|
+ addr2line_print(print_info[PRINT_UFSR_NOCP]);
|
|
|
380
|
+ }
|
|
|
381
|
+ if (regs.ufsr.bits.UNALIGNED)
|
|
|
382
|
+ {
|
|
|
383
|
+ addr2line_print(print_info[PRINT_UFSR_UNALIGNED]);
|
|
|
384
|
+ }
|
|
|
385
|
+ if (regs.ufsr.bits.DIVBYZERO0)
|
|
|
386
|
+ {
|
|
|
387
|
+ addr2line_print(print_info[PRINT_UFSR_DIVBYZERO0]);
|
|
|
388
|
+ }
|
|
|
389
|
+ }
|
|
|
390
|
+ }
|
|
|
391
|
+ /* Debug Fault */
|
|
|
392
|
+ if (regs.hfsr.bits.DEBUGEVT)
|
|
|
393
|
+ {
|
|
|
394
|
+ if (regs.dfsr.value)
|
|
|
395
|
+ {
|
|
|
396
|
+ if (regs.dfsr.bits.HALTED)
|
|
|
397
|
+ {
|
|
|
398
|
+ addr2line_print(print_info[PRINT_DFSR_HALTED]);
|
|
|
399
|
+ }
|
|
|
400
|
+ if (regs.dfsr.bits.BKPT)
|
|
|
401
|
+ {
|
|
|
402
|
+ addr2line_print(print_info[PRINT_DFSR_BKPT]);
|
|
|
403
|
+ }
|
|
|
404
|
+ if (regs.dfsr.bits.DWTTRAP)
|
|
|
405
|
+ {
|
|
|
406
|
+ addr2line_print(print_info[PRINT_DFSR_DWTTRAP]);
|
|
|
407
|
+ }
|
|
|
408
|
+ if (regs.dfsr.bits.VCATCH)
|
|
|
409
|
+ {
|
|
|
410
|
+ addr2line_print(print_info[PRINT_DFSR_VCATCH]);
|
|
|
411
|
+ }
|
|
|
412
|
+ if (regs.dfsr.bits.EXTERNAL)
|
|
|
413
|
+ {
|
|
|
414
|
+ addr2line_print(print_info[PRINT_DFSR_EXTERNAL]);
|
|
|
415
|
+ }
|
|
|
416
|
+ }
|
|
|
417
|
+ }
|
|
|
418
|
+}
|
|
|
419
|
+#endif
|
|
|
420
|
+
|
|
|
421
|
+int coredump_fault_diagnosis(void)
|
|
|
422
|
+{
|
|
|
423
|
+ /* the Cortex-M0 is not support fault diagnosis */
|
|
|
424
|
+#if (DUMP_CPU_PLATFORM_TYPE != DUMP_CPU_ARM_CORTEX_M0)
|
|
|
425
|
+ regs.syshndctrl.value = DUMP_SYSHND_CTRL; // System Handler Control and State Register
|
|
|
426
|
+ regs.mfsr.value = DUMP_NVIC_MFSR; // Memory Fault Status Register
|
|
|
427
|
+ regs.mmar = DUMP_NVIC_MMAR; // Memory Management Fault Address Register
|
|
|
428
|
+ regs.bfsr.value = DUMP_NVIC_BFSR; // Bus Fault Status Register
|
|
|
429
|
+ regs.bfar = DUMP_NVIC_BFAR; // Bus Fault Manage Address Register
|
|
|
430
|
+ regs.ufsr.value = DUMP_NVIC_UFSR; // Usage Fault Status Register
|
|
|
431
|
+ regs.hfsr.value = DUMP_NVIC_HFSR; // Hard Fault Status Register
|
|
|
432
|
+ regs.dfsr.value = DUMP_NVIC_DFSR; // Debug Fault Status Register
|
|
|
433
|
+ regs.afsr = DUMP_NVIC_AFSR; // Auxiliary Fault Status Register
|
|
|
434
|
+
|
|
|
435
|
+ fault_diagnosis();
|
|
|
436
|
+ return 0;
|
|
|
437
|
+#endif
|
|
|
438
|
+
|
|
|
439
|
+ return -1;
|
|
|
440
|
+}
|
|
|
441
|
+
|
|
|
442
|
+int addr2line_print_stack_before(uint32_t exc_return)
|
|
|
443
|
+{
|
|
|
444
|
+ int on_thread_before_fault = exc_return & (1UL << 2);
|
|
|
445
|
+ /* check which stack was used before (MSP or PSP) */
|
|
|
446
|
+ if (on_thread_before_fault)
|
|
|
447
|
+ addr2line_print(print_info[PRINT_FAULT_ON_THREAD], rt_thread_self()->name != NULL ? rt_thread_self()->name : "NO_NAME");
|
|
|
448
|
+ else
|
|
|
449
|
+ addr2line_print(print_info[PRINT_FAULT_ON_HANDLER]);
|
|
|
450
|
+
|
|
|
451
|
+ coredump_fault_diagnosis();
|
|
|
452
|
+ return 0;
|
|
|
453
|
+}
|
|
|
454
|
+
|
|
|
455
|
+void addr2line_trigger_exception(void)
|
|
|
456
|
+{
|
|
|
457
|
+ volatile int *SCB_CCR = (volatile int *)0xE000ED14; // SCB->CCR
|
|
|
458
|
+ int x, y, z;
|
|
|
459
|
+
|
|
|
460
|
+ *SCB_CCR |= (1 << 4); /* bit4: DIV_0_TRP. */
|
|
|
461
|
+ x = 10;
|
|
|
462
|
+ y = strlen("");
|
|
|
463
|
+ z = x / y;
|
|
|
464
|
+ addr2line_print("z:%d\n", z);
|
|
|
465
|
+}
|
|
|
466
|
+
|
|
|
467
|
+
|
|
|
468
|
+// addr to line
|
|
|
469
|
+#include <stdbool.h>
|
|
|
470
|
+
|
|
|
471
|
+#pragma section = ".text"
|
|
|
472
|
+
|
|
|
473
|
+static bool is_in_text(uint32_t addr)
|
|
|
474
|
+{
|
|
|
475
|
+#if 0
|
|
|
476
|
+ uint32_t code_start_addr = (uint32_t)&CODE_SECTION_START(CMB_CODE_SECTION_NAME);
|
|
|
477
|
+ uint32_t code_size = (uint32_t)&CODE_SECTION_END(CMB_CODE_SECTION_NAME) - code_start_addr;
|
|
|
478
|
+#else
|
|
|
479
|
+ uint32_t code_start_addr = (uint32_t)__section_begin(".text");
|
|
|
480
|
+ uint32_t code_size = (uint32_t)__section_end(".text") - code_start_addr;
|
|
|
481
|
+#endif
|
|
|
482
|
+
|
|
|
483
|
+ if (code_start_addr < addr && addr <= code_start_addr + code_size)
|
|
|
484
|
+ {
|
|
|
485
|
+ return true;
|
|
|
486
|
+ }
|
|
|
487
|
+
|
|
|
488
|
+ return false;
|
|
|
489
|
+}
|
|
|
490
|
+
|
|
|
491
|
+static bool disassembly_ins_is_bl_blx(uint32_t addr)
|
|
|
492
|
+{
|
|
|
493
|
+#define BL_INS_MASK 0xF800
|
|
|
494
|
+#define BL_INS_HIGH 0xF800
|
|
|
495
|
+#define BL_INS_LOW 0xF000
|
|
|
496
|
+#define BLX_INX_MASK 0xFF00
|
|
|
497
|
+#define BLX_INX 0x4700
|
|
|
498
|
+
|
|
|
499
|
+ uint16_t ins1 = *((uint16_t *)addr);
|
|
|
500
|
+ uint16_t ins2 = *((uint16_t *)(addr + 2));
|
|
|
501
|
+
|
|
|
502
|
+ if ((ins2 & BL_INS_MASK) == BL_INS_HIGH && (ins1 & BL_INS_MASK) == BL_INS_LOW)
|
|
|
503
|
+ {
|
|
|
504
|
+ return true;
|
|
|
505
|
+ }
|
|
|
506
|
+ else if ((ins2 & BLX_INX_MASK) == BLX_INX)
|
|
|
507
|
+ {
|
|
|
508
|
+ return true;
|
|
|
509
|
+ }
|
|
|
510
|
+ else
|
|
|
511
|
+ {
|
|
|
512
|
+ return false;
|
|
|
513
|
+ }
|
|
|
514
|
+}
|
|
|
515
|
+
|
|
|
516
|
+void addr2line_cmd_with_pc_print(uint32_t *thread_pc, uint32_t *addr, int size)
|
|
|
517
|
+{
|
|
|
518
|
+ addr2line_print("addr2line -e " PROJECT_NAME " -a -f ");
|
|
|
519
|
+ size /= sizeof(uint32_t);
|
|
|
520
|
+
|
|
|
521
|
+ if (thread_pc)
|
|
|
522
|
+ addr2line_print("%08x ", thread_pc);
|
|
|
523
|
+
|
|
|
524
|
+ for (int i = 1; i < size; i++)
|
|
|
525
|
+ {
|
|
|
526
|
+ const uint32_t lr = addr[i];
|
|
|
527
|
+
|
|
|
528
|
+ if (false == is_in_text(lr))
|
|
|
529
|
+ continue;
|
|
|
530
|
+
|
|
|
531
|
+ uint32_t pc = lr - sizeof(size_t); // 假设当前是lr寄存器的值，向下增长4就是pc寄存器的值
|
|
|
532
|
+
|
|
|
533
|
+ if (pc % 2 == 0) // thumb 指令pc寄存器值一定是偶数
|
|
|
534
|
+ continue;
|
|
|
535
|
+
|
|
|
536
|
+
|
|
|
537
|
+ pc = lr - 1; // lr寄存器值保存的是pc+1
|
|
|
538
|
+
|
|
|
539
|
+ if ((uint32_t)thread_pc == pc) // 忽略：已经指定打印过了
|
|
|
540
|
+ continue;
|
|
|
541
|
+
|
|
|
542
|
+ if (true == disassembly_ins_is_bl_blx(pc - sizeof(size_t))) // pc 的上一条指令是跳转指令
|
|
|
543
|
+ addr2line_print("%08x ", pc);
|
|
|
544
|
+ }
|
|
|
545
|
+
|
|
|
546
|
+ addr2line_print("\n\n");
|
|
|
547
|
+}
|
|
|
548
|
+
|
|
|
549
|
+void addr2line_cmd_print(uint32_t *addr, int size)
|
|
|
550
|
+{
|
|
|
551
|
+ addr2line_cmd_with_pc_print(NULL, addr, size);
|
|
|
552
|
+}
|
|
|
553
|
+
|
|
|
554
|
+#if 0
|
|
|
555
|
+static void test_addr2line(void)
|
|
|
556
|
+{
|
|
|
557
|
+ uint32_t sg_test_stack[] =
|
|
|
558
|
+ {
|
|
|
559
|
+ 0x00000001, 0x000514d5, 0x000000f0, 0x00000001,
|
|
|
560
|
+ 0x000c3fcc, 0x00000000, 0x000538b4, 0x00549822,
|
|
|
561
|
+ 0xdeadbeef, 0x00000000, 0x00000000, 0x00000000,
|
|
|
562
|
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
|
|
|
563
|
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
|
|
|
564
|
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
|
|
|
565
|
+ 0x00000000, 0x0000000a, 0x00000210, 0x00000000,
|
|
|
566
|
+ 0x00000000, 0x00000006, 0x000514eb, 0x000516f8,
|
|
|
567
|
+ 0x49000000, 0x00000004, 0x0000007d, 0x00000000,
|
|
|
568
|
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
|
|
|
569
|
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
|
|
|
570
|
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
|
|
|
571
|
+ 0x00000000, 0x00000010, 0x00000000, 0x00000200,
|
|
|
572
|
+ 0x00000000, 0x000008f4, 0x000537bb, 0x000000f0,
|
|
|
573
|
+ 0x00000000, 0x00000001, 0x00000002, 0x20033378,
|
|
|
574
|
+ 0x000468e3, 0x00000000, 0x20036c3c, 0x20036c78,
|
|
|
575
|
+ 0x000b8789, 0x00000000, 0x20016dd8, 0x20008198,
|
|
|
576
|
+ 0x000b819f, 0x00000000, 0x2003727c, 0x20016dd8,
|
|
|
577
|
+ 0x0006047f, 0x00000050, 0x00000000, 0x20016dd8,
|
|
|
578
|
+ 0x00000001, 0x00000001, 0x000604dd, 0x00000000,
|
|
|
579
|
+ 0x2003092c, 0x20030b1c, 0x200334f4, 0x200334b4,
|
|
|
580
|
+ 0x00060215, 0x2003764c, 0x20036e98, 0x00000008,
|
|
|
581
|
+ 0x200081f4, 0x200334b4, 0x00000000, 0x0068007a,
|
|
|
582
|
+ 0x00000000, 0x20030b1c, 0x00063dd3, 0x007a0068,
|
|
|
583
|
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
|
|
|
584
|
+ 0xffffffff, 0x20033520, 0x2003060c, 0x2002cc84,
|
|
|
585
|
+ 0x2002cbf4, 0x20033378, 0x0005ce35, 0x20030e20,
|
|
|
586
|
+ 0x000d17c8, 0x20030214, 0x00000014, 0xdeadbeef,
|
|
|
587
|
+ 0xdeadbeef, 0xdeadbeef, 0x00057c99, 0x00000000,
|
|
|
588
|
+ 0xdeadbeef, 0xdeadbeef, 0xdeadbeef, 0xdeadbeef,
|
|
|
589
|
+ 0x000302e7
|
|
|
590
|
+ };
|
|
|
591
|
+
|
|
|
592
|
+ uint32_t *addr = sg_test_stack;
|
|
|
593
|
+ int size = sizeof(sg_test_stack);
|
|
|
594
|
+ _addr2line_print(addr, size);
|
|
|
595
|
+}
|
|
|
596
|
+#endif
|
