[add] MCoreDump

EWARM/stm32_broad_mini.ewp

@@ -220,6 +220,8 @@
                     <name>CCDefines</name>
                     <state>USE_HAL_DRIVER</state>
                     <state>STM32F103xB</state>
+                    <state>__RTTHREAD__</state>
+                    <state>PKG_USING_MCOREDUMP_ARCH_ARMV7M</state>
                 </option>
                 <option>
                     <name>CCPreprocFile</name>
@@ -353,6 +355,10 @@
                     <state>$PROJ_DIR$/../Middlewares/rtthread/include</state>
                     <state>$PROJ_DIR$/../Middlewares/rtthread/include/libc</state>
                     <state>$PROJ_DIR$/../Middlewares/rtthread/finsh</state>
+                    <state>$PROJ_DIR$/../Middlewares/MCoreDump/src/arm</state>
+                    <state>$PROJ_DIR$/../Middlewares/MCoreDump/inc</state>
+                    <state>$PROJ_DIR$/../Middlewares/MCoreDump/arch</state>
+                    <state>$PROJ_DIR$/../Middlewares/MCoreDump/arch/armv7m</state>
                 </option>
                 <option>
                     <name>CCStdIncCheck</name>
@@ -1176,6 +1182,9 @@
         <name>Middlewares</name>
         <group>
             <name>coredump</name>
+            <excluded>
+                <configuration>stm32_broad_mini</configuration>
+            </excluded>
             <file>
                 <name>$PROJ_DIR$\..\Middlewares\coredump\coredump.c</name>
             </file>
@@ -1222,6 +1231,36 @@
                 <name>$PROJ_DIR$\..\Middlewares\Third_Party\FreeRTOS\Source\timers.c</name>
             </file>
         </group>
+        <group>
+            <name>MCoreDump</name>
+            <group>
+                <name>arch</name>
+                <file>
+                    <name>$PROJ_DIR$\..\Middlewares\MCoreDump\arch\armv7m\armv7m.c</name>
+                </file>
+            </group>
+            <group>
+                <name>osal</name>
+                <file>
+                    <name>$PROJ_DIR$\..\Middlewares\MCoreDump\osal\rtthread.c</name>
+                </file>
+            </group>
+            <group>
+                <name>src</name>
+                <file>
+                    <name>$PROJ_DIR$\..\Middlewares\MCoreDump\src\coredump.c</name>
+                </file>
+                <file>
+                    <name>$PROJ_DIR$\..\Middlewares\MCoreDump\src\faultdump.c</name>
+                </file>
+                <file>
+                    <name>$PROJ_DIR$\..\Middlewares\MCoreDump\src\arm\mcd_arm.c</name>
+                </file>
+            </group>
+            <file>
+                <name>$PROJ_DIR$\..\Middlewares\MCoreDump\example\mcd_example.c</name>
+            </file>
+        </group>
         <group>
             <name>RTT</name>
             <file>

Middlewares/MCoreDump/arch/armv7m/armv7m.c

@@ -0,0 +1,379 @@
+/*
+ * Copyright (c) 2025, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2025-08-16     Rbb666       first version
+ */
+
+#include "coredump.h"
+#include "registers.h"
+
+#define FPU_CPACR 0xE000ED88
+
+int is_vfp_addressable(void)
+{
+    uint32_t reg_cpacr = *((volatile uint32_t *)FPU_CPACR);
+    if (reg_cpacr & 0x00F00000)
+        return 1;
+    else
+        return 0;
+}
+
+#if defined(__CC_ARM)
+
+/* clang-format off */
+__asm void mcd_mini_dump()
+{
+    extern get_cur_core_regset_address;
+    extern get_cur_fp_regset_address;
+    extern mcd_mini_dump_ops;
+    extern mcd_gen_coredump;
+    extern is_vfp_addressable;
+
+    PRESERVE8
+
+    push {r7, lr}
+    sub sp, sp, #24
+    add r7, sp, #0
+
+get_regset
+    bl get_cur_core_regset_address
+    str r0, [r0, #0]
+    add r0, r0, #4
+    stmia r0!, {r1 - r12}
+    mov r1, sp
+    add r1, #32
+    str r1, [r0, #0]
+    ldr r1, [sp, #28]
+    str r1, [r0, #4]
+    mov r1, pc
+    str r1, [r0, #8]
+    mrs r1, xpsr
+    str r1, [r0, #12]
+
+    bl is_vfp_addressable
+    cmp r0, #0
+    beq get_reg_done
+
+    bl get_cur_fp_regset_address
+    vstmia r0!, {d0 - d15}
+    vmrs r1, fpscr
+    str r1, [r0, #0]
+
+get_reg_done
+    mov r0, r7
+    bl mcd_mini_dump_ops
+    mov r0, r7
+    bl mcd_gen_coredump
+    nop
+    adds r7, r7, #24
+    mov sp, r7
+    pop {r7, pc}
+    nop
+    nop
+}
+
+__asm void mcd_multi_dump(void)
+{
+    extern get_cur_core_regset_address;
+    extern get_cur_fp_regset_address;
+    extern mcd_rtos_thread_ops;
+    extern mcd_gen_coredump;
+    extern is_vfp_addressable;
+
+    PRESERVE8
+
+    push {r7, lr}
+    sub sp, sp, #24
+    add r7, sp, #0
+
+get_regset1
+    bl get_cur_core_regset_address
+    str r0, [r0, #0]
+    add r0, r0, #4
+    stmia r0!, {r1 - r12}
+    mov r1, sp
+    add r1, #32
+    str r1, [r0, #0]
+    ldr r1, [sp, #28]
+    str r1, [r0, #4]
+    mov r1, pc
+    str r1, [r0, #8]
+    mrs r1, xpsr
+    str r1, [r0, #12]
+
+    bl is_vfp_addressable
+    cmp r0, #0
+    beq get_reg_done
+
+    bl get_cur_fp_regset_address
+    vstmia r0!, {d0 - d15}
+    vmrs r1, fpscr
+    str r1, [r0, #0]
+
+get_reg_done1
+    mov r0, r7
+    bl mcd_rtos_thread_ops
+    mov r0, r7
+    bl mcd_gen_coredump
+    nop
+    adds r7, r7, #24
+    mov sp, r7
+    pop {r7, pc}
+    nop
+    nop
+}
+
+#elif 1//defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) || defined(__GNUC__)
+
+#define mcd_get_regset(regset)                                              \
+    __asm volatile("  mov r0, %0                \n"                         \
+                   "  str r0, [r0 , #0]         \n"                         \
+                   "  add r0, r0, #4            \n"                         \
+                   "  stmia  r0!, {r1 - r12}    \n"                         \
+                   "  mov r1, sp                \n"                         \
+                   "  str  r1, [r0, #0]         \n"                         \
+                   "  mov r1, lr                \n"                         \
+                   "  str  r1, [r0, #4]         \n"                         \
+                   "  mov r1, pc                \n"                         \
+                   "  str  r1, [r0, #8]         \n"                         \
+                   "  mrs r1, xpsr              \n"                         \
+                   "  str  r1, [r0, #12]        \n" ::"r"(regset)           \
+                   : "memory", "cc");
+
+#define mcd_get_fpregset(regset)                                            \
+    __asm volatile(" mov r0, %0                 \n"                         \
+                   " vstmia r0!, {d0 - d15}     \n"                         \
+                   " vmrs r1, fpscr             \n"                         \
+                   " str  r1, [r0, #0]          \n" ::"r"(regset)           \
+                   : "memory", "cc");
+
+void mcd_mini_dump(void)
+{
+    struct thread_info_ops ops;
+
+    mcd_get_regset((uint32_t *)get_cur_core_regset_address());
+
+#if MCD_FPU_SUPPORT
+    if (is_vfp_addressable())
+        mcd_get_fpregset((uint32_t *)get_cur_fp_regset_address());
+#endif
+
+    mcd_mini_dump_ops(&ops);
+    mcd_gen_coredump(&ops);
+}
+
+void mcd_multi_dump(void)
+{
+    struct thread_info_ops ops;
+
+    mcd_get_regset((uint32_t *)get_cur_core_regset_address());
+
+#if MCD_FPU_SUPPORT
+    if (is_vfp_addressable())
+        mcd_get_fpregset((uint32_t *)get_cur_fp_regset_address());
+#endif
+
+    mcd_rtos_thread_ops(&ops);
+    mcd_gen_coredump(&ops);
+}
+
+#endif
+
+/**
+ * @brief Collect ARM Cortex-M4 registers from RT-Thread stack frame
+ *
+ * This function extracts register values from the stack frame created by
+ * RT-Thread's context switch mechanism (PendSV_Handler) or exception handling.
+ *
+ * RT-Thread Stack Frame Layout (from low to high memory address):
+ * +-------------------+  <- stack_top (input parameter)
+ * | FPU flag          |  (4 bytes, if MCD_FPU_SUPPORT enabled)
+ * +-------------------+
+ * | r4                |  (4 bytes, software saved)
+ * | r5                |  (4 bytes, software saved)
+ * | r6                |  (4 bytes, software saved)
+ * | r7                |  (4 bytes, software saved)
+ * | r8                |  (4 bytes, software saved)
+ * | r9                |  (4 bytes, software saved)
+ * | r10               |  (4 bytes, software saved)
+ * | r11               |  (4 bytes, software saved)
+ * +-------------------+
+ * | FPU s16-s31       |  (64 bytes, if FPU context active)
+ * +-------------------+
+ * | r0                |  (4 bytes, hardware saved)
+ * | r1                |  (4 bytes, hardware saved)
+ * | r2                |  (4 bytes, hardware saved)
+ * | r3                |  (4 bytes, hardware saved)
+ * | r12               |  (4 bytes, hardware saved)
+ * | lr                |  (4 bytes, hardware saved)
+ * | pc                |  (4 bytes, hardware saved)
+ * | xpsr              |  (4 bytes, hardware saved)
+ * +-------------------+
+ * | FPU s0-s15        |  (64 bytes, if FPU context active)
+ * | FPSCR             |  (4 bytes, if FPU context active)
+ * | NO_NAME           |  (4 bytes, if FPU context active)
+ * +-------------------+  <- current SP after context save
+ *
+ * @param stack_top Pointer to the beginning of the stack frame (FPU flag position)
+ * @param core_regset Pointer to structure for storing ARM core registers
+ * @param fp_regset Pointer to structure for storing FPU registers
+ */
+void collect_registers_armv7m(uint32_t *stack_top,
+                                    core_regset_type *core_regset,
+                                    fp_regset_type *fp_regset)
+{
+    /*
+     * This function uses the same stack frame parsing approach as collect_registers_armv7ms
+     * for consistency. Both PendSV_Handler and HardFault_Handler now use identical
+     * stacking order after the modifications.
+     *
+     * Expected stack layout starting from stack_top:
+     * [FPU flag] -> [r4-r11] -> [FPU s16-s31] -> [exception frame] -> [FPU s0-s15,FPSCR]
+     */
+    uint32_t *current_ptr = stack_top;
+
+    /* Clear both register sets first to ensure clean state */
+    mcd_memset(core_regset, 0, sizeof(core_regset_type));
+    mcd_memset(fp_regset, 0, sizeof(fp_regset_type));
+
+#if MCD_FPU_SUPPORT
+    /* Read FPU flag first - indicates if FPU context was saved */
+    uint32_t fpu_flag = *current_ptr++;
+#endif
+
+    /* Extract core registers r4-r11 (software saved by RT-Thread) */
+    core_regset->r4 = *current_ptr++;
+    core_regset->r5 = *current_ptr++;
+    core_regset->r6 = *current_ptr++;
+    core_regset->r7 = *current_ptr++;
+    core_regset->r8 = *current_ptr++;
+    core_regset->r9 = *current_ptr++;
+    core_regset->r10 = *current_ptr++;
+    core_regset->r11 = *current_ptr++;
+
+#if MCD_FPU_SUPPORT
+    /* If FPU context is active, s16-s31 registers are saved after r4-r11 */
+    if (fpu_flag)
+    {
+        /* Copy FPU s16-s31 registers (software saved by RT-Thread) */
+        for (int i = 16; i < 32; i++)
+        {
+            ((uint32_t *)fp_regset)[i] = *current_ptr++;
+        }
+    }
+#endif
+
+    /* Extract hardware exception frame (automatically saved by ARM Cortex-M) */
+    core_regset->r0 = *current_ptr++;
+    core_regset->r1 = *current_ptr++;
+    core_regset->r2 = *current_ptr++;
+    core_regset->r3 = *current_ptr++;
+    core_regset->r12 = *current_ptr++;
+    core_regset->lr = *current_ptr++;
+    core_regset->pc = *current_ptr++;
+    core_regset->xpsr = *current_ptr++;
+
+#if MCD_FPU_SUPPORT
+    /* If FPU context is active, s0-s15 and FPSCR are saved after exception frame */
+    if (fpu_flag)
+    {
+        /* Copy FPU s0-s15 registers (hardware saved by ARM Cortex-M) */
+        for (int i = 0; i < 16; i++)
+        {
+            ((uint32_t *)fp_regset)[i] = *current_ptr++;
+        }
+
+        /* Copy FPSCR register (FPU status and control) */
+        fp_regset->fpscr = *current_ptr++;
+
+        /* Skip NO_NAME field (reserved/alignment) */
+        current_ptr++;
+    }
+#endif
+
+    /* SP should point to the current stack pointer position after all saved data */
+    core_regset->sp = (uintptr_t)current_ptr;
+}
+
+/**
+ * @brief ARM Cortex-M specific hard fault exception handler for MCoreDump
+ *
+ * This function handles ARM Cortex-M specific stack frame processing when a
+ * hard fault occurs. It calculates the proper stack pointer position and
+ * extracts register context for coredump generation.
+ *
+ * HardFault Stack Frame Layout (created by HardFault_Handler):
+ * +-------------------+  <- Exception occurs here
+ * | Hardware Exception|  (32 bytes: r0,r1,r2,r3,r12,lr,pc,xpsr)
+ * | Stack Frame       |  (+ optional 72 bytes FPU: s0-s15,FPSCR,NO_NAME)
+ * +-------------------+  <- context parameter points here
+ * | r11               |  (4 bytes, software saved in HardFault_Handler)
+ * | r10               |  (4 bytes, software saved in HardFault_Handler)
+ * | ...               |  (...)
+ * | r4                |  (4 bytes, software saved in HardFault_Handler)
+ * +-------------------+
+ * | FPU s31           |  (4 bytes, if FPU context active)
+ * | FPU s30           |  (4 bytes, if FPU context active)
+ * | ...               |  (...)
+ * | FPU s16           |  (4 bytes, if FPU context active)
+ * +-------------------+
+ * | FPU flag          |  (4 bytes, if MCD_FPU_SUPPORT enabled)
+ * +-------------------+
+ * | EXC_RETURN        |  (4 bytes, contains exception return information)
+ * +-------------------+  <- Final stack pointer position
+ *
+ * @param context Pointer to exception_stack_frame from HardFault_Handler
+ * @return int Always returns -1 to indicate fault condition
+ */
+int armv7m_hard_fault_exception_hook(void *context)
+{
+    /*
+     * context points to exception_stack_frame created by HardFault_Handler.
+     * We need to calculate the complete stack frame position to extract all registers.
+     * Since HardFault_Handler now uses the same stacking order as PendSV_Handler,
+     * we can directly use collect_registers_armv7m function.
+     */
+
+    struct exception_stack_frame *exception_stack = (struct exception_stack_frame *)context;
+
+    /* Calculate stack pointer to the beginning of the saved context */
+    uint32_t *stack_ptr = (uint32_t *)exception_stack;
+
+#ifdef RT_USING_FINSH
+    extern long list_thread(void);
+    list_thread();
+#endif
+
+    /*
+     * Move backward through the stack to reach the beginning of saved context.
+     * Stack layout (working backwards from exception_stack):
+     * exception_stack -> r4-r11 (8 words) -> [s16-s31] -> [fpu_flag] -> [exc_return]
+     */
+    stack_ptr -= 8; /* Move backward 8 uint32_t positions to reach r4 */
+
+#if MCD_FPU_SUPPORT
+    /* Point to FPU flag position (collect_registers_armv7m expects this as start) */
+    stack_ptr -= 1; /* fpu flag */
+#else
+    /* If no FPU support, skip EXC_RETURN and point to r4 directly */
+    stack_ptr -= 1; /* exc_return */
+#endif
+
+    /*
+     * Now stack_ptr points to where collect_registers_armv7m expects:
+     * - With FPU: points to FPU flag (first field to be read)
+     * - Without FPU: points to r4 (first register to be read)
+     */
+    collect_registers_armv7m(stack_ptr,
+                           get_cur_core_regset_address(),
+                           get_cur_fp_regset_address());
+
+    /* Generate coredump using memory mode */
+    mcd_faultdump(MCD_OUTPUT_MEMORY);
+
+    return 0;
+}

Middlewares/MCoreDump/arch/armv7m/registers.h

@@ -0,0 +1,69 @@
+/*
+ * Copyright (c) 2025, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2025-08-16     Rbb666       first version
+ */
+
+#ifndef __REGISTERS_H__
+#define __REGISTERS_H__
+
+#include <stdint.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+struct armv7m_core_regset
+{
+    uint32_t r0;
+    uint32_t r1;
+    uint32_t r2;
+    uint32_t r3;
+    uint32_t r4;
+    uint32_t r5;
+    uint32_t r6;
+    uint32_t r7;
+    uint32_t r8;
+    uint32_t r9;
+    uint32_t r10;
+    uint32_t r11;
+    uint32_t r12;
+    uint32_t sp;
+    uint32_t lr;
+    uint32_t pc;
+    uint32_t xpsr;
+};
+
+struct arm_vfpv2_regset
+{
+    uint64_t d0;
+    uint64_t d1;
+    uint64_t d2;
+    uint64_t d3;
+    uint64_t d4;
+    uint64_t d5;
+    uint64_t d6;
+    uint64_t d7;
+    uint64_t d8;
+    uint64_t d9;
+    uint64_t d10;
+    uint64_t d11;
+    uint64_t d12;
+    uint64_t d13;
+    uint64_t d14;
+    uint64_t d15;
+    uint32_t fpscr;
+};
+
+typedef struct armv7m_core_regset    core_regset_type;
+typedef struct arm_vfpv2_regset      fp_regset_type;
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __MCD_REGISTERS_H__ */

Middlewares/MCoreDump/arch/armv8m/armv8m.c

@@ -0,0 +1,394 @@
+/*
+ * Copyright (c) 2025, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2025-08-16     Rbb666       first version
+ */
+
+#include "coredump.h"
+#include "registers.h"
+
+#define FPU_CPACR 0xE000ED88
+
+int is_vfp_addressable(void)
+{
+    uint32_t reg_cpacr = *((volatile uint32_t *)FPU_CPACR);
+    if (reg_cpacr & 0x00F00000)
+        return 1;
+    else
+        return 0;
+}
+
+#if defined(__CC_ARM)
+
+/* clang-format off */
+__asm void mcd_mini_dump()
+{
+    extern get_cur_core_regset_address;
+    extern get_cur_fp_regset_address;
+    extern mcd_mini_dump_ops;
+    extern mcd_gen_coredump;
+    extern is_vfp_addressable;
+
+    PRESERVE8
+
+    push {r7, lr}
+    sub sp, sp, #24
+    add r7, sp, #0
+
+get_regset
+    bl get_cur_core_regset_address
+    str r0, [r0, #0]
+    add r0, r0, #4
+    stmia r0!, {r1 - r12}
+    mov r1, sp
+    add r1, #32
+    str r1, [r0, #0]
+    ldr r1, [sp, #28]
+    str r1, [r0, #4]
+    mov r1, pc
+    str r1, [r0, #8]
+    mrs r1, xpsr
+    str r1, [r0, #12]
+
+    bl is_vfp_addressable
+    cmp r0, #0
+    beq get_reg_done
+
+    bl get_cur_fp_regset_address
+    vstmia r0!, {d0 - d15}
+    vmrs r1, fpscr
+    str r1, [r0, #0]
+
+get_reg_done
+    mov r0, r7
+    bl mcd_mini_dump_ops
+    mov r0, r7
+    bl mcd_gen_coredump
+    nop
+    adds r7, r7, #24
+    mov sp, r7
+    pop {r7, pc}
+    nop
+    nop
+}
+
+__asm void mcd_multi_dump(void)
+{
+    extern get_cur_core_regset_address;
+    extern get_cur_fp_regset_address;
+    extern mcd_rtos_thread_ops;
+    extern mcd_gen_coredump;
+    extern is_vfp_addressable;
+
+    PRESERVE8
+
+    push {r7, lr}
+    sub sp, sp, #24
+    add r7, sp, #0
+
+get_regset1
+    bl get_cur_core_regset_address
+    str r0, [r0, #0]
+    add r0, r0, #4
+    stmia r0!, {r1 - r12}
+    mov r1, sp
+    add r1, #32
+    str r1, [r0, #0]
+    ldr r1, [sp, #28]
+    str r1, [r0, #4]
+    mov r1, pc
+    str r1, [r0, #8]
+    mrs r1, xpsr
+    str r1, [r0, #12]
+
+    bl is_vfp_addressable
+    cmp r0, #0
+    beq get_reg_done
+
+    bl get_cur_fp_regset_address
+    vstmia r0!, {d0 - d15}
+    vmrs r1, fpscr
+    str r1, [r0, #0]
+
+get_reg_done1
+    mov r0, r7
+    bl mcd_rtos_thread_ops
+    mov r0, r7
+    bl mcd_gen_coredump
+    nop
+    adds r7, r7, #24
+    mov sp, r7
+    pop {r7, pc}
+    nop
+    nop
+}
+
+#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) || defined(__GNUC__)
+
+#define mcd_get_regset(regset)                                              \
+    __asm volatile("  mov r0, %0                \n"                         \
+                   "  str r0, [r0 , #0]         \n"                         \
+                   "  add r0, r0, #4            \n"                         \
+                   "  stmia  r0!, {r1 - r12}    \n"                         \
+                   "  mov r1, sp                \n"                         \
+                   "  str  r1, [r0, #0]         \n"                         \
+                   "  mov r1, lr                \n"                         \
+                   "  str  r1, [r0, #4]         \n"                         \
+                   "  mov r1, pc                \n"                         \
+                   "  str  r1, [r0, #8]         \n"                         \
+                   "  mrs r1, xpsr              \n"                         \
+                   "  str  r1, [r0, #12]        \n" ::"r"(regset)           \
+                   : "memory", "cc");
+
+#define mcd_get_fpregset(regset)                                            \
+    __asm volatile(" mov r0, %0                 \n"                         \
+                   " vstmia r0!, {d0 - d15}     \n"                         \
+                   " vmrs r1, fpscr             \n"                         \
+                   " str  r1, [r0, #0]          \n" ::"r"(regset)           \
+                   : "memory", "cc");
+
+void mcd_mini_dump(void)
+{
+    struct thread_info_ops ops;
+
+    mcd_get_regset((uint32_t *)get_cur_core_regset_address());
+
+#if MCD_FPU_SUPPORT
+    if (is_vfp_addressable())
+        mcd_get_fpregset((uint32_t *)get_cur_fp_regset_address());
+#endif
+
+    mcd_mini_dump_ops(&ops);
+    mcd_gen_coredump(&ops);
+}
+
+void mcd_multi_dump(void)
+{
+    struct thread_info_ops ops;
+
+    mcd_get_regset((uint32_t *)get_cur_core_regset_address());
+
+#if MCD_FPU_SUPPORT
+    if (is_vfp_addressable())
+        mcd_get_fpregset((uint32_t *)get_cur_fp_regset_address());
+#endif
+
+    mcd_rtos_thread_ops(&ops);
+    mcd_gen_coredump(&ops);
+}
+
+#endif
+
+/**
+ * @brief Collect ARM Cortex-M33 registers from RT-Thread stack frame
+ *
+ * This function extracts register values from the stack frame created by
+ * RT-Thread's HardFault_Handler for ARMv8-M architecture.
+ * 
+ * ARMv8-M Stack Frame Layout (based on HardFault_Handler in context_gcc.S):
+ * +-------------------+  <- stack_top (input parameter)
+ * | EXC_RETURN        |  (4 bytes, contains exception return information)
+ * +-------------------+
+ * | tz                |  (4 bytes, TrustZone context)
+ * | lr                |  (4 bytes, saved link register)
+ * | psplim            |  (4 bytes, stack pointer limit)
+ * | control           |  (4 bytes, control register)
+ * +-------------------+
+ * | r4                |  (4 bytes, software saved)
+ * | r5                |  (4 bytes, software saved)
+ * | r6                |  (4 bytes, software saved)
+ * | r7                |  (4 bytes, software saved)
+ * | r8                |  (4 bytes, software saved)
+ * | r9                |  (4 bytes, software saved)
+ * | r10               |  (4 bytes, software saved)
+ * | r11               |  (4 bytes, software saved)
+ * +-------------------+
+ * | FPU d8-d15        |  (64 bytes, if FPU context active)
+ * +-------------------+
+ * | r0                |  (4 bytes, hardware saved)
+ * | r1                |  (4 bytes, hardware saved)
+ * | r2                |  (4 bytes, hardware saved)
+ * | r3                |  (4 bytes, hardware saved)
+ * | r12               |  (4 bytes, hardware saved)
+ * | lr                |  (4 bytes, hardware saved)
+ * | pc                |  (4 bytes, hardware saved)
+ * | xpsr              |  (4 bytes, hardware saved)
+ * +-------------------+
+ * | FPU d0-d7         |  (64 bytes, if FPU context active)
+ * | FPSCR             |  (4 bytes, if FPU context active)
+ * | NO_NAME           |  (4 bytes, if FPU context active)
+ * +-------------------+  <- current SP after context save
+ *
+ * @param stack_top Pointer to the beginning of the stack frame (EXC_RETURN position)
+ * @param core_regset Pointer to structure for storing ARM core registers
+ * @param fp_regset Pointer to structure for storing FPU registers
+ */
+void collect_registers_armv8m(uint32_t *stack_top,
+                                    core_regset_type *core_regset,
+                                    fp_regset_type *fp_regset)
+{    
+    /* 
+     * ARMv8-M has two different stack layouts:
+     * 1. Exception context (HardFault_Handler): [EXC_RETURN] -> [tz,lr,psplim,control] -> [r4-r11] -> [FPU d8-d15] -> [exception frame] -> [FPU d0-d7,FPSCR]
+     * 2. Normal thread context (PendSV_Handler): [tz,lr,psplim,control] -> [r4-r11] -> [hardware exception frame]
+     */
+    uint32_t *current_ptr = stack_top;
+    
+    /* Clear both register sets first to ensure clean state */ 
+    mcd_memset(core_regset, 0, sizeof(core_regset_type));
+    mcd_memset(fp_regset, 0, sizeof(fp_regset_type));
+
+    /* Read first word to determine context type */
+    uint32_t first_word = *current_ptr;
+    uint32_t fpu_flag = 0;  // Default to no FPU context
+    
+    /* Check if this is a valid EXC_RETURN value (starts with 0xFF) */
+    if ((first_word & 0xFF000000) == 0xFF000000) 
+    {
+        /* Valid EXC_RETURN - this is an exception context */
+        uint32_t exc_return = *current_ptr++;
+        fpu_flag = !(exc_return & 0x10);
+        /* Skip tz, lr, psplim, control fields (4 words) */
+        current_ptr += 4;
+    }
+    else 
+    {
+        /* Not a valid EXC_RETURN - this is normal thread context from PendSV_Handler */
+        fpu_flag = 0;
+        /* For normal thread context, stack_top points to [tz,lr,psplim,control] */
+        /* Skip tz, lr, psplim, control fields (4 words) */
+        current_ptr += 4;
+    }
+
+    /* Extract core registers r4-r11 (software saved by RT-Thread) */
+    core_regset->r4 = *current_ptr++;
+    core_regset->r5 = *current_ptr++;
+    core_regset->r6 = *current_ptr++;
+    core_regset->r7 = *current_ptr++;
+    core_regset->r8 = *current_ptr++;
+    core_regset->r9 = *current_ptr++;
+    core_regset->r10 = *current_ptr++;
+    core_regset->r11 = *current_ptr++;
+
+#if MCD_FPU_SUPPORT
+    /* If FPU context is active, d8-d15 registers are saved after r4-r11 */
+    if (fpu_flag)
+    {
+        /* Copy FPU d8-d15 registers (software saved by HardFault_Handler) */
+        /* Each double precision register is 64 bits = 2 words */
+        uint64_t *fp_d_ptr = (uint64_t *)current_ptr;
+        for (int i = 0; i < 8; i++)  /* d8-d15 = 8 registers */
+        {
+            (&fp_regset->d8)[i] = *fp_d_ptr++;
+        }
+        current_ptr = (uint32_t *)fp_d_ptr;
+    }
+#endif
+
+    /* Extract hardware exception frame (automatically saved by ARM Cortex-M) */
+    core_regset->r0 = *current_ptr++;
+    core_regset->r1 = *current_ptr++;
+    core_regset->r2 = *current_ptr++;
+    core_regset->r3 = *current_ptr++;
+    core_regset->r12 = *current_ptr++;
+    core_regset->lr = *current_ptr++;
+    core_regset->pc = *current_ptr++;
+    core_regset->xpsr = *current_ptr++;
+
+#if MCD_FPU_SUPPORT
+    /* If FPU context is active, d0-d7 and FPSCR are saved after exception frame */
+    if (fpu_flag)
+    {
+        /* Copy FPU d0-d7 registers (hardware saved by ARM Cortex-M) */
+        /* Each double precision register is 64 bits = 2 words */
+        uint64_t *fp_d_ptr = (uint64_t *)current_ptr;
+        for (int i = 0; i < 8; i++)  /* d0-d7 = 8 registers */
+        {
+            (&fp_regset->d0)[i] = *fp_d_ptr++;
+        }
+        current_ptr = (uint32_t *)fp_d_ptr;
+        
+        /* Copy FPSCR register (FPU status and control) */
+        fp_regset->fpscr = *current_ptr++;
+        
+        /* Skip NO_NAME field (reserved/alignment) */
+        current_ptr++;
+    }
+#endif
+
+    /* SP should point to the current stack pointer position after all saved data */
+    core_regset->sp = (uintptr_t)current_ptr;
+}
+
+/**
+ * @brief ARM Cortex-M33 specific hard fault exception handler for MCoreDump
+ * 
+ * This function handles ARM Cortex-M33 specific stack frame processing when a 
+ * hard fault occurs. It follows the armv7m approach for simple and reliable
+ * stack pointer calculation.
+ * 
+ * HardFault Stack Frame Layout (created by HardFault_Handler):
+ * +-------------------+  <- Exception occurs here
+ * | Hardware Exception|  (32 bytes: r0,r1,r2,r3,r12,lr,pc,xpsr)
+ * | Stack Frame       |  (+ optional 72 bytes FPU: s0-s15,FPSCR,NO_NAME)
+ * +-------------------+  <- context parameter points here
+ * | r11               |  (4 bytes, software saved in HardFault_Handler)
+ * | r10               |  (4 bytes, software saved in HardFault_Handler)
+ * | ...               |  (...)
+ * | r4                |  (4 bytes, software saved in HardFault_Handler)
+ * +-------------------+
+ * | FPU s31           |  (4 bytes, if FPU context active)
+ * | FPU s30           |  (4 bytes, if FPU context active)
+ * | ...               |  (...)
+ * | FPU s16           |  (4 bytes, if FPU context active)
+ * +-------------------+
+ * | FPU flag          |  (4 bytes, if MCD_FPU_SUPPORT enabled)
+ * +-------------------+  <- Target position for collect_registers_armv8m
+ *
+ * @param context Pointer to exception_stack_frame from HardFault_Handler
+ * @return int Always returns 0 after processing coredump
+ */
+int armv8m_hard_fault_exception_hook(void *context)
+{
+    /* Add debug output to confirm we reach this function */
+    mcd_print("armv8m_hard_fault_exception_hook called, context = 0x%08x\n", (uint32_t)context);
+    
+    /* 
+     * Based on HardFault_Handler implementation in context_gcc.S:
+     * 
+     * For EXCEPTION context (HardFault_Handler):
+     * Stack layout from context (exception_stack_frame) backwards:
+     * context -> [r0,r1,r2,r3,r12,lr,pc,xpsr] (exception frame)
+     * context-32 -> [r11,r10,r9,r8,r7,r6,r5,r4] (8 words, STMFD r0!, {r4-r11})
+     * context-48 -> [tz,lr,psplim,control] (4 words, STMFD r0!, {r2-r5})  
+     * context-52 -> [EXC_RETURN] (1 word, STMFD r0!, {lr})
+     * 
+     * We need to point to EXC_RETURN for collect_registers_armv8m
+     */
+
+    uint32_t *stack_ptr = (uint32_t *)context;
+    
+    /* Move backwards to find EXC_RETURN position */
+    stack_ptr -= 8;  /* r4-r11 (8 registers) */
+    stack_ptr -= 4;  /* tz, lr, psplim, control (4 fields) */  
+    stack_ptr -= 1;  /* EXC_RETURN */
+
+#ifdef RT_USING_FINSH
+    extern long list_thread(void);
+    list_thread();
+#endif
+
+    /* Now stack_ptr points to EXC_RETURN, which is what collect_registers_armv8m expects */
+    collect_registers_armv8m(stack_ptr,
+                           get_cur_core_regset_address(),
+                           get_cur_fp_regset_address());
+
+    /* Generate coredump using memory mode */
+    mcd_faultdump(MCD_OUTPUT_MEMORY);
+
+    return 0;
+}

Middlewares/MCoreDump/arch/armv8m/registers.h

@@ -0,0 +1,69 @@
+/*
+ * Copyright (c) 2025, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2025-08-16     Rbb666       first version
+ */
+
+#ifndef __REGISTERS_H__
+#define __REGISTERS_H__
+
+#include <stdint.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+struct armv8m_core_regset
+{
+    uint32_t r0;
+    uint32_t r1;
+    uint32_t r2;
+    uint32_t r3;
+    uint32_t r4;
+    uint32_t r5;
+    uint32_t r6;
+    uint32_t r7;
+    uint32_t r8;
+    uint32_t r9;
+    uint32_t r10;
+    uint32_t r11;
+    uint32_t r12;
+    uint32_t sp;
+    uint32_t lr;
+    uint32_t pc;
+    uint32_t xpsr;
+};
+
+struct arm_vfpv2_regset
+{
+    uint64_t d0;
+    uint64_t d1;
+    uint64_t d2;
+    uint64_t d3;
+    uint64_t d4;
+    uint64_t d5;
+    uint64_t d6;
+    uint64_t d7;
+    uint64_t d8;
+    uint64_t d9;
+    uint64_t d10;
+    uint64_t d11;
+    uint64_t d12;
+    uint64_t d13;
+    uint64_t d14;
+    uint64_t d15;
+    uint32_t fpscr;
+};
+
+typedef struct armv8m_core_regset    core_regset_type;
+typedef struct arm_vfpv2_regset      fp_regset_type;
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __MCD_REGISTERS_H__ */

Middlewares/MCoreDump/arch/mcd_arch_interface.h

@@ -0,0 +1,67 @@
+/*
+ * Copyright (c) 2025, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2025-08-16     Rbb666       first version
+ */
+
+#ifndef __MCD_ARCH_INTERFACE_H__
+#define __MCD_ARCH_INTERFACE_H__
+
+#include <stdint.h>
+
+/**
+ * @brief Architecture-specific hard fault exception handler
+ * 
+ * This function should be implemented by each supported architecture
+ * to handle the architecture-specific stack frame processing.
+ * 
+ * @param context Pointer to exception context (architecture-specific format)
+ * @return int Always returns -1 to indicate fault condition
+ */
+#ifdef PKG_USING_MCOREDUMP_ARCH_ARMV7M
+int armv7m_hard_fault_exception_hook(void *context);
+
+/**
+ * @brief Architecture-specific register collection function
+ * 
+ * This function extracts register values from the architecture-specific
+ * stack frame format and stores them in the standard register sets.
+ * 
+ * @param stack_top Pointer to the stack frame
+ * @param core_regset Pointer to store ARM core registers  
+ * @param fp_regset Pointer to store FPU registers
+ */
+void collect_registers_armv7m(uint32_t *stack_top,
+                             core_regset_type *core_regset,
+                             fp_regset_type *fp_regset);
+
+/* Generic interface macro for architecture-agnostic code */
+#define collect_registers collect_registers_armv7m
+#endif
+
+#ifdef PKG_USING_MCOREDUMP_ARCH_ARMV8M
+int armv8m_hard_fault_exception_hook(void *context);
+
+/**
+ * @brief Architecture-specific register collection function
+ * 
+ * This function extracts register values from the architecture-specific
+ * stack frame format and stores them in the standard register sets.
+ * 
+ * @param stack_top Pointer to the stack frame
+ * @param core_regset Pointer to store ARM core registers  
+ * @param fp_regset Pointer to store FPU registers
+ */
+void collect_registers_armv8m(uint32_t *stack_top,
+                             core_regset_type *core_regset,
+                             fp_regset_type *fp_regset);
+
+/* Generic interface macro for architecture-agnostic code */
+#define collect_registers collect_registers_armv8m
+#endif
+
+#endif /* __MCD_ARCH_INTERFACE_H__ */

Middlewares/MCoreDump/example/mcd_example.c

@@ -0,0 +1,69 @@
+/*
+ * Copyright (c) 2025, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2025-08-16     Rbb666       first version
+ */
+
+#include <math.h>
+#include <stdlib.h>
+#include <string.h>
+#include "coredump.h"
+
+typedef void (*fault_func)(float);
+
+static int mcd_test(int argc, char **argv)
+{
+    int x, y;
+    const char * sx = "84597";
+    const char * sy = "35268";
+
+    float a, b, c;
+    const char * fsa = "1.1322";
+    const char * fsb = "45.2547";
+    const char * fsc = "7854.2";
+
+    if (argc < 2)
+    {
+        rt_kprintf("Please input 'mcd_test <COREDUMP|ASSERT|FAULT>' \n");
+        return 0;
+    }
+
+    if (!strcmp(argv[1], "COREDUMP"))
+    {
+        mcd_faultdump(MCD_OUTPUT_SERIAL);
+        return 0;
+    }
+    else if (!strcmp(argv[1], "ASSERT"))
+    {
+        a = atof(&fsa[0]);
+        b = atof(&fsb[0]);
+        c = atof(&fsc[0]);
+
+        x = atoi(&sx[0]);
+        y = atoi(&sy[0]);
+
+        mcd_assert(x * a == y * b * c);
+        return 0;
+    }
+    else if (!strcmp(argv[1], "FAULT"))
+    {
+        fault_func func = (fault_func)0xFFFF0000;
+        
+        a = atof(&fsa[0]);
+        b = atof(&fsb[0]);
+        c = atof(&fsc[0]);
+
+        x = atoi(&sx[0]);
+        y = atoi(&sy[0]);
+
+        func(x * a + y * b * c);
+        return 0;
+    }
+    
+    return 0;
+}
+MCD_CMD_EXPORT(mcd_test, mCoreDump test: mcd_test <COREDUMP|FLOAT|ASSERT|FAULT>);

Middlewares/MCoreDump/inc/coredump.h

@@ -0,0 +1,245 @@
+/*
+ * Copyright (c) 2025, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2025-08-16     Rbb666       first version
+ */
+
+#ifndef __COREDUMP_H__
+#define __COREDUMP_H__
+
+#include "mcd_cfg.h"
+#include "mcd_arm_define.h"
+
+/**
+ * @brief Function pointer type for coredump data output
+ * 
+ * This function pointer type defines the interface for writing coredump data
+ * to different output destinations (memory, serial, filesystem, etc.).
+ * 
+ * @param data Pointer to the data buffer to be written
+ * @param len Length of the data buffer in bytes
+ * 
+ * @note The implementation should handle the data appropriately based on the
+ *       chosen output mode and ensure data integrity.
+ */
+typedef void (*mcd_writeout_func_t)(uint8_t *, int);
+
+/**
+ * @brief Thread information operations structure
+ * 
+ * This structure contains function pointers for retrieving thread information
+ * in a RTOS environment. It's designed to avoid dynamic memory allocation
+ * during fault handling, as malloc operations may fail during hard faults.
+ * 
+ * The structure provides a generic interface for different RTOS systems
+ * to supply thread information for multi-threaded coredump generation.
+ */
+struct thread_info_ops
+{
+    /**
+     * @brief Get total number of threads in the system
+     * @param ops Pointer to this operations structure
+     * @return Total thread count
+     */
+    int32_t (*get_threads_count)(struct thread_info_ops *);
+    
+    /**
+     * @brief Get current executing thread index
+     * @param ops Pointer to this operations structure  
+     * @return Current thread index
+     */
+    int32_t (*get_current_thread_idx)(struct thread_info_ops *);
+    
+    /**
+     * @brief Get register set for a specific thread
+     * @param ops Pointer to this operations structure
+     * @param thread_idx Thread index to get registers for
+     * @param core_regset Pointer to store ARM core registers
+     * @param fp_regset Pointer to store FPU registers
+     */
+    void (*get_thread_regset)(struct thread_info_ops *, int32_t,
+                              core_regset_type *core_regset,
+                              fp_regset_type *fp_regset);
+    
+    /**
+     * @brief Get number of memory areas to dump
+     * @param ops Pointer to this operations structure
+     * @return Number of memory areas
+     */
+    int32_t (*get_memarea_count)(struct thread_info_ops *);
+    
+    /**
+     * @brief Get memory area information
+     * @param ops Pointer to this operations structure
+     * @param area_idx Memory area index
+     * @param addr Pointer to store memory area start address
+     * @param size Pointer to store memory area size
+     * @return 0 on success, negative on error
+     */
+    int32_t (*get_memarea)(struct thread_info_ops *, int32_t,
+                           uint32_t *, uint32_t *);
+    
+    /** Private data for RTOS-specific implementations */
+    void *priv;
+};
+
+/**
+ * @brief Initialize the mCoreDump system
+ *
+ * This function initializes the mCoreDump system with automatic FPU detection.
+ * It must be called before any coredump generation operations.
+ *
+ * FPU support is automatically detected based on compiler definitions:
+ * - Enabled if __VFP_FP__ is defined and __SOFTFP__ is not defined
+ * - Disabled if no hardware FPU support is detected
+ *
+ * @param func Function pointer to write the coredump data out.
+ *             This callback will be called repeatedly with chunks of coredump data.
+ *
+ * @note The writeout function should handle data appropriately based on the
+ *       chosen output mode (memory, serial, filesystem).
+ *
+ * @warning This function should be called from a safe context, preferably
+ *          during system initialization or before fault occurs.
+ *
+ * @see mcd_writeout_func_t for callback function requirements
+ */
+void mcd_init(mcd_writeout_func_t func);
+
+/**
+ * @brief Generate coredump for current call chain only
+ *
+ * This function generates a minimal coredump containing only the current
+ * execution context (single thread). It's faster and uses less memory
+ * compared to multi-threaded coredump generation.
+ *
+ * Use this function when:
+ * - Quick fault analysis is needed
+ * - Memory is limited
+ * - Only current thread context is relevant
+ *
+ * @note This function captures the current thread's register state and
+ *       stack information at the point of call.
+ *
+ * @warning Must call mcd_init() before using this function.
+ *
+ * @see mcd_multi_dump() for full system coredump
+ */
+void mcd_mini_dump(void);
+
+/**
+ * @brief Generate coredump with all threads information
+ *
+ * This function generates a comprehensive coredump containing information
+ * about all threads in the system, including their register states,
+ * stack contents, and memory areas.
+ *
+ * Use this function when:
+ * - Complete system state analysis is needed
+ * - Multi-threading issues need to be debugged
+ * - Full context switch information is required
+ *
+ * @note This function may take longer to execute and use more memory
+ *       compared to mcd_mini_dump().
+ *
+ * @warning Must call mcd_init() before using this function.
+ *          Should be used carefully in interrupt context due to execution time.
+ *
+ * @see mcd_mini_dump() for single thread coredump
+ */
+void mcd_multi_dump(void);
+
+/**
+ * @brief Generate coredump using provided thread operations
+ *
+ * This is the core coredump generation function that uses the provided
+ * thread_info_ops structure to gather system information and generate
+ * the ELF format coredump.
+ *
+ * @param ops Pointer to thread information operations structure.
+ *            Contains function pointers for retrieving thread and memory information.
+ *
+ * @note This is a low-level function typically called by mcd_mini_dump()
+ *       and mcd_multi_dump() after setting up appropriate ops structure.
+ *
+ * @warning The ops structure must be properly initialized with valid
+ *          function pointers before calling this function.
+ */
+void mcd_gen_coredump(struct thread_info_ops *ops);
+
+/**
+ * @brief Setup thread operations for RTOS environment
+ *
+ * This function initializes the thread_info_ops structure with function
+ * pointers appropriate for the current RTOS environment (RT-Thread).
+ *
+ * @param ops Pointer to thread operations structure to be initialized
+ *
+ * @note This function is typically called internally by mcd_multi_dump()
+ *       to set up multi-threaded coredump generation.
+ */
+void mcd_rtos_thread_ops(struct thread_info_ops *ops);
+
+/**
+ * @brief Setup thread operations for single thread dump
+ *
+ * This function initializes the thread_info_ops structure for minimal
+ * coredump generation (current thread only).
+ *
+ * @param ops Pointer to thread operations structure to be initialized
+ *
+ * @note This function is typically called internally by mcd_mini_dump()
+ *       to set up single-threaded coredump generation.
+ */
+void mcd_mini_dump_ops(struct thread_info_ops *ops);
+
+/**
+ * @brief           Generate coredump and save to specified output.
+ *
+ * @param[in]       output_mode Output mode (MCD_OUTPUT_SERIAL, MCD_OUTPUT_MEMORY, or MCD_OUTPUT_FILESYSTEM).
+ *
+ * @return          Whether save operation success.
+ * @retval          MCD_OK      success.
+ * @retval          MCD_ERROR   failed.
+ */
+int mcd_faultdump(mcd_output_mode_t output_mode);
+
+/**
+ * @brief Print coredump memory information at startup
+ *
+ * This function should be called during system initialization
+ */
+void mcd_print_memoryinfo(void);
+
+/**
+ * @brief Get address of current core register set
+ *
+ * This function returns a pointer to the current thread's core register
+ * set storage area. The register values are captured during fault handling.
+ *
+ * @return Pointer to core register set structure
+ *
+ * @note The returned pointer points to static storage that gets updated
+ *       each time a fault occurs or registers are captured.
+ */
+core_regset_type *get_cur_core_regset_address(void);
+
+/**
+ * @brief Get address of current floating-point register set
+ *
+ * This function returns a pointer to the current thread's floating-point
+ * register set storage area. The register values are captured during fault handling.
+ *
+ * @return Pointer to floating-point register set structure
+ *
+ * @note The returned pointer points to static storage that gets updated
+ *       each time a fault occurs or registers are captured.
+ *       Returns valid data only if FPU is available and enabled.
+ */
+fp_regset_type *get_cur_fp_regset_address(void);
+
+#endif /* __MCOREDUMP_H__ */

Middlewares/MCoreDump/inc/mcd_cfg.h

@@ -0,0 +1,229 @@
+/*
+ * Copyright (c) 2025, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2025-08-16     Rbb666       Configuration file for mCoreDump
+ */
+
+#ifndef __MCD_CFG_H__
+#define __MCD_CFG_H__
+
+/*
+ * ===============================================================
+ * Operating System Detection and Abstraction Layer
+ * ===============================================================
+ */
+
+/* Auto-detect operating system */
+#ifdef __RTTHREAD__
+    #define MCD_OS_RTTHREAD    1
+    #include <rtthread.h>
+#else
+    #define MCD_OS_BAREMETAL   1
+    #include <stdint.h>
+    #include <stdbool.h>
+#endif
+
+#define MCD_ALIGN(x, y)  (((x - 1) / y + 1) * y)
+
+/*
+ * ===============================================================
+ * Print configuration - Printf function abstraction
+ * ===============================================================
+ */
+
+/* OS-specific print function abstraction */
+#ifdef MCD_OS_RTTHREAD
+/* RT-Thread print functions */
+#ifndef RT_USING_ULOG
+/* Use rt_kprintf directly */
+#define mcd_println(...)               rt_kprintf(__VA_ARGS__);rt_kprintf("\r\n")
+#define mcd_print(...)                 rt_kprintf(__VA_ARGS__)
+#else /* RT_USING_ULOG */
+/* Use ulog for unified logging */
+#include <ulog.h>
+#define MCD_LOG_TAG                    "mcd"
+#define mcd_println(...)               ulog_e(MCD_LOG_TAG, __VA_ARGS__);ulog_flush()
+#define mcd_print(...)                 ulog_raw(__VA_ARGS__)
+#endif /* RT_USING_ULOG */
+#else
+/* Bare metal - use standard printf or define custom */
+#include <stdio.h>
+#define mcd_println(...)               printf(__VA_ARGS__);printf("\r\n")
+#define mcd_print(...)                 printf(__VA_ARGS__)
+#endif /* MCD_OS_RTTHREAD */
+
+/*
+ * ===============================================================
+ * Memory management abstraction
+ * ===============================================================
+ */
+
+#ifdef MCD_OS_RTTHREAD
+#define mcd_malloc(size)               rt_malloc(size)
+#define mcd_free(ptr)                  rt_free(ptr)
+#define mcd_memset(ptr, val, size)     rt_memset(ptr, val, size)
+#define mcd_memcpy(dst, src, size)     rt_memcpy(dst, src, size)
+#else
+/* Standard C library */
+#include <stdlib.h>
+#include <string.h>
+#define mcd_malloc(size)               malloc(size)
+#define mcd_free(ptr)                  free(ptr)
+#define mcd_memset(ptr, val, size)     memset(ptr, val, size)
+#define mcd_memcpy(dst, src, size)     memcpy(dst, src, size)
+#endif
+
+/*
+ * ===============================================================
+ * Interrupt control abstraction
+ * ===============================================================
+ */
+
+#ifdef MCD_OS_RTTHREAD
+typedef rt_base_t mcd_irq_state_t;
+#define mcd_irq_disable()              rt_hw_interrupt_disable()
+#define mcd_irq_enable(state)          rt_hw_interrupt_enable(state)
+#else
+/* Bare metal - define as needed for specific platform */
+typedef uint32_t mcd_irq_state_t;
+#define mcd_irq_disable()              __disable_irq();
+#define mcd_irq_enable(state)          __enable_irq()
+#endif
+
+/*
+ * ===============================================================
+ * Command export abstraction
+ * ===============================================================
+ */
+
+#ifdef MCD_OS_RTTHREAD
+#define MCD_CMD_EXPORT(cmd, desc)      MSH_CMD_EXPORT(cmd, desc)
+#else
+/* Other OS or bare metal */
+#define MCD_CMD_EXPORT(cmd, desc)      /* No command export */
+#endif
+
+/*
+ * ===============================================================
+ * Boolean type abstraction
+ * ===============================================================
+ */
+
+#ifdef MCD_OS_RTTHREAD
+#define mcd_bool_t                     rt_bool_t
+#define MCD_TRUE                       RT_TRUE
+#define MCD_FALSE                      RT_FALSE
+#else
+#include <stdbool.h>
+#define mcd_bool_t                     bool
+#define MCD_TRUE                       true
+#define MCD_FALSE                      false
+#endif
+
+/*
+ * ===============================================================
+ * ASSERT type abstraction
+ * ===============================================================
+ */
+
+#ifdef MCD_OS_RTTHREAD
+#define mcd_assert(expr)               RT_ASSERT(expr)
+#else
+#include <assert.h>
+#define mcd_assert(expr)               assert(expr)
+#endif /* MCD_OS_RTTHREAD */
+
+/*
+ * ===============================================================
+ * Weak attribute abstraction
+ * ===============================================================
+ */
+
+#ifdef MCD_OS_RTTHREAD
+#ifndef RT_WEAK
+#define MCD_WEAK                   rt_weak
+#else
+#define MCD_WEAK                   RT_WEAK
+#endif /* RT_WEAK */
+#else
+/* Standard GCC weak attribute */
+#define MCD_WEAK                       __attribute__((weak))
+#endif /* MCD_OS_RTTHREAD */
+
+/*
+ * ===============================================================
+ * Floating Point Unit (FPU) configuration
+ * ===============================================================
+ */
+
+/* Automatic FPU detection - based on compiler definitions */
+#if	/* ARMCC */ (  (defined ( __CC_ARM ) && defined ( __TARGET_FPU_VFP ))    \
+	/* Clang */ || (defined ( __clang__ ) && defined ( __VFP_FP__ ) && !defined(__SOFTFP__)) \
+	/* IAR */   || (defined ( __ICCARM__ ) && defined ( __ARMVFP__ ))        \
+	/* GNU */   || (defined ( __GNUC__ ) && defined ( __VFP_FP__ ) && !defined(__SOFTFP__)) )
+#define MCD_FPU_SUPPORT          1    /* FPU supported and enabled */
+#else
+#define MCD_FPU_SUPPORT          0    /* No FPU support */
+#endif
+
+/*
+ * ===============================================================
+ * Memory configuration
+ * ===============================================================
+ */
+
+/* Default memory buffer size (can be overridden by Kconfig) */
+#ifndef PKG_MCOREDUMP_MEMORY_SIZE
+#define MCD_DEFAULT_MEMORY_SIZE           (8 * 1024)    /* Default 8KB */
+#else
+#define MCD_DEFAULT_MEMORY_SIZE           PKG_MCOREDUMP_MEMORY_SIZE
+#endif /* PKG_MCOREDUMP_MEMORY_SIZE */
+
+/*
+ * ===============================================================
+ * Filesystem configuration
+ * ===============================================================
+ */
+
+#ifdef PKG_USING_MCOREDUMP_FILESYSTEM
+/* Default filesystem settings */
+#ifndef PKG_MCOREDUMP_FILESYSTEM_DIR
+#define MCD_DEFAULT_COREDUMP_DIR      "/sdcard"
+#else
+#define MCD_DEFAULT_COREDUMP_DIR      PKG_MCOREDUMP_FILESYSTEM_DIR
+#endif /* PKG_MCOREDUMP_FILESYSTEM_DIR*/
+
+#ifndef PKG_MCOREDUMP_FILESYSTEM_PREFIX
+#define MCD_DEFAULT_COREDUMP_PREFIX   "core_"
+#else
+#define MCD_DEFAULT_COREDUMP_PREFIX   PKG_MCOREDUMP_FILESYSTEM_PREFIX
+#endif /* PKG_MCOREDUMP_FILESYSTEM_PREFIX */
+
+#define MCD_DEFAULT_COREDUMP_EXT          ".elf"
+#endif /* PKG_USING_MCOREDUMP_FILESYSTEM */
+
+/*
+ * ===============================================================
+ * Output mode definitions
+ * ===============================================================
+ */
+
+/* Coredump output modes */
+typedef enum {
+    MCD_OUTPUT_SERIAL = 0,                /* Output via serial port */
+    MCD_OUTPUT_MEMORY,                    /* Store in memory buffer */
+    MCD_OUTPUT_FILESYSTEM,                /* Save to filesystem */
+    MCD_OUTPUT_FLASH                      /* Store in flash (reserved) */
+} mcd_output_mode_t;
+
+/* Return codes */
+enum {
+    MCD_ERROR = -1,
+    MCD_OK = 0,
+};
+
+#endif /* __MCD_CFG_H__ */

Middlewares/MCoreDump/inc/mcd_elf_define.h

@@ -0,0 +1,472 @@
+/*
+ * Copyright (c) 2025, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2025-08-16     Rbb666       first version
+ */
+
+#ifndef __MCD_ELF_DEFINE_H__
+#define __MCD_ELF_DEFINE_H__
+
+/* Fields in e_ident[].  */
+#define EI_MAG0 0    /* File identification byte 0 index */
+#define ELFMAG0 0x7F /* Magic number byte 0 */
+
+#define EI_MAG1 1   /* File identification byte 1 index */
+#define ELFMAG1 'E' /* Magic number byte 1 */
+
+#define EI_MAG2 2   /* File identification byte 2 index */
+#define ELFMAG2 'L' /* Magic number byte 2 */
+
+#define EI_MAG3 3   /* File identification byte 3 index */
+#define ELFMAG3 'F' /* Magic number byte 3 */
+
+#define EI_CLASS 4     /* File class */
+#define ELFCLASSNONE 0 /* Invalid class */
+#define ELFCLASS32 1   /* 32-bit objects */
+#define ELFCLASS64 2   /* 64-bit objects */
+
+#define EI_DATA 5     /* Data encoding */
+#define ELFDATANONE 0 /* Invalid data encoding */
+#define ELFDATA2LSB 1 /* 2's complement, little endian */
+#define ELFDATA2MSB 2 /* 2's complement, big endian */
+
+#define EI_VERSION 6 /* File version */
+
+#define EI_OSABI 7           /* Operating System/ABI indication */
+#define ELFOSABI_NONE 0      /* UNIX System V ABI */
+#define ELFOSABI_HPUX 1      /* HP-UX operating system */
+#define ELFOSABI_NETBSD 2    /* NetBSD */
+#define ELFOSABI_GNU 3       /* GNU */
+#define ELFOSABI_LINUX 3     /* Alias for ELFOSABI_GNU */
+#define ELFOSABI_SOLARIS 6   /* Solaris */
+#define ELFOSABI_AIX 7       /* AIX */
+#define ELFOSABI_IRIX 8      /* IRIX */
+#define ELFOSABI_FREEBSD 9   /* FreeBSD */
+#define ELFOSABI_TRU64 10    /* TRU64 UNIX */
+#define ELFOSABI_MODESTO 11  /* Novell Modesto */
+#define ELFOSABI_OPENBSD 12  /* OpenBSD */
+#define ELFOSABI_OPENVMS 13  /* OpenVMS */
+#define ELFOSABI_NSK 14      /* Hewlett-Packard Non-Stop Kernel */
+#define ELFOSABI_AROS 15     /* AROS */
+#define ELFOSABI_FENIXOS 16  /* FenixOS */
+#define ELFOSABI_CLOUDABI 17 /* Nuxi CloudABI */
+#define ELFOSABI_OPENVOS 18  /* Stratus Technologies OpenVOS */
+
+#define ELFOSABI_C6000_ELFABI 64 /* Bare-metal TMS320C6000 */
+#define ELFOSABI_C6000_LINUX 65  /* Linux TMS320C6000 */
+#define ELFOSABI_ARM_FDPIC 65    /* ARM FDPIC */
+#define ELFOSABI_ARM 97          /* ARM */
+#define ELFOSABI_STANDALONE 255  /* Standalone (embedded) application */
+
+#define EI_ABIVERSION 8 /* ABI version */
+
+#define EI_PAD 9 /* Start of padding bytes */
+
+#define EI_NIDENT 16
+
+/* Values for e_type, which identifies the object file type.  */
+
+#define ET_NONE 0 /* No file type */
+#define ET_REL 1  /* Relocatable file */
+#define ET_EXEC 2 /* Position-dependent executable file */
+#define ET_DYN                                                                 \
+  3                      /* Position-independent executable or                 \
+                    shared object file */
+#define ET_CORE 4        /* Core file */
+#define ET_LOOS 0xFE00   /* Operating system-specific */
+#define ET_HIOS 0xFEFF   /* Operating system-specific */
+#define ET_LOPROC 0xFF00 /* Processor-specific */
+#define ET_HIPROC 0xFFFF /* Processor-specific */
+
+/* Values for e_machine, which identifies the architecture.  These numbers
+   are officially assigned by registry@sco.com.  See below for a list of
+   ad-hoc numbers used during initial development.  */
+
+#define EM_NONE 0  /* No machine */
+#define EM_M32 1   /* AT&T WE 32100 */
+#define EM_SPARC 2 /* SUN SPARC */
+#define EM_386 3   /* Intel 80386 */
+#define EM_68K 4   /* Motorola m68k family */
+#define EM_88K 5   /* Motorola m88k family */
+#define EM_IAMCU 6 /* Intel MCU */
+#define EM_860 7   /* Intel 80860 */
+#define EM_MIPS 8  /* MIPS R3000 (officially, big-endian only) */
+#define EM_S370 9  /* IBM System/370 */
+#define EM_MIPS_RS3_LE                                                         \
+  10 /* MIPS R3000 little-endian (Oct 4 1999 Draft).  Deprecated.  */
+#define EM_OLD_SPARCV9                                                         \
+  11 /* Old version of Sparc v9, from before the ABI.  Deprecated.  */
+#define EM_res011 11      /* Reserved */
+#define EM_res012 12      /* Reserved */
+#define EM_res013 13      /* Reserved */
+#define EM_res014 14      /* Reserved */
+#define EM_PARISC 15      /* HPPA */
+#define EM_res016 16      /* Reserved */
+#define EM_PPC_OLD 17     /* Old version of PowerPC.  Deprecated.  */
+#define EM_VPP550 17      /* Fujitsu VPP500 */
+#define EM_SPARC32PLUS 18 /* Sun's "v8plus" */
+#define EM_960 19         /* Intel 80960 */
+#define EM_PPC 20         /* PowerPC */
+#define EM_PPC64 21       /* 64-bit PowerPC */
+#define EM_S390 22        /* IBM S/390 */
+#define EM_SPU 23         /* Sony/Toshiba/IBM SPU */
+#define EM_res024 24      /* Reserved */
+#define EM_res025 25      /* Reserved */
+#define EM_res026 26      /* Reserved */
+#define EM_res027 27      /* Reserved */
+#define EM_res028 28      /* Reserved */
+#define EM_res029 29      /* Reserved */
+#define EM_res030 30      /* Reserved */
+#define EM_res031 31      /* Reserved */
+#define EM_res032 32      /* Reserved */
+#define EM_res033 33      /* Reserved */
+#define EM_res034 34      /* Reserved */
+#define EM_res035 35      /* Reserved */
+#define EM_V800 36        /* NEC V800 series */
+#define EM_FR20 37        /* Fujitsu FR20 */
+#define EM_RH32 38        /* TRW RH32 */
+#define EM_MCORE                                                               \
+  39 /* Motorola M*Core */ /* May also be taken by Fujitsu MMA                 \
+                            */
+#define EM_RCE 39          /* Old name for MCore */
+#define EM_ARM 40          /* ARM */
+#define EM_OLD_ALPHA 41    /* Digital Alpha */
+#define EM_SH 42           /* Renesas (formerly Hitachi) / SuperH SH */
+#define EM_SPARCV9 43      /* SPARC v9 64-bit */
+#define EM_TRICORE 44      /* Siemens Tricore embedded processor */
+#define EM_ARC 45          /* ARC Cores */
+#define EM_H8_300 46       /* Renesas (formerly Hitachi) H8/300 */
+#define EM_H8_300H 47      /* Renesas (formerly Hitachi) H8/300H */
+#define EM_H8S 48          /* Renesas (formerly Hitachi) H8S */
+#define EM_H8_500 49       /* Renesas (formerly Hitachi) H8/500 */
+#define EM_IA_64 50        /* Intel IA-64 Processor */
+#define EM_MIPS_X 51       /* Stanford MIPS-X */
+#define EM_COLDFIRE 52     /* Motorola Coldfire */
+#define EM_68HC12 53       /* Motorola M68HC12 */
+#define EM_MMA 54          /* Fujitsu Multimedia Accelerator */
+#define EM_PCP 55          /* Siemens PCP */
+#define EM_NCPU 56         /* Sony nCPU embedded RISC processor */
+#define EM_NDR1 57         /* Denso NDR1 microprocessor */
+#define EM_STARCORE 58     /* Motorola Star*Core processor */
+#define EM_ME16 59         /* Toyota ME16 processor */
+#define EM_ST100 60        /* STMicroelectronics ST100 processor */
+#define EM_TINYJ 61        /* Advanced Logic Corp. TinyJ embedded processor */
+#define EM_X86_64 62       /* Advanced Micro Devices X86-64 processor */
+#define EM_PDSP 63         /* Sony DSP Processor */
+#define EM_PDP10 64        /* Digital Equipment Corp. PDP-10 */
+#define EM_PDP11 65        /* Digital Equipment Corp. PDP-11 */
+#define EM_FX66 66         /* Siemens FX66 microcontroller */
+#define EM_ST9PLUS 67     /* STMicroelectronics ST9+ 8/16 bit microcontroller */
+#define EM_ST7 68         /* STMicroelectronics ST7 8-bit microcontroller */
+#define EM_68HC16 69      /* Motorola MC68HC16 Microcontroller */
+#define EM_68HC11 70      /* Motorola MC68HC11 Microcontroller */
+#define EM_68HC08 71      /* Motorola MC68HC08 Microcontroller */
+#define EM_68HC05 72      /* Motorola MC68HC05 Microcontroller */
+#define EM_SVX 73         /* Silicon Graphics SVx */
+#define EM_ST19 74        /* STMicroelectronics ST19 8-bit cpu */
+#define EM_VAX 75         /* Digital VAX */
+#define EM_CRIS 76        /* Axis Communications 32-bit embedded processor */
+#define EM_JAVELIN 77     /* Infineon Technologies 32-bit embedded cpu */
+#define EM_FIREPATH 78    /* Element 14 64-bit DSP processor */
+#define EM_ZSP 79         /* LSI Logic's 16-bit DSP processor */
+#define EM_MMIX 80        /* Donald Knuth's educational 64-bit processor */
+#define EM_HUANY 81       /* Harvard's machine-independent format */
+#define EM_PRISM 82       /* SiTera Prism */
+#define EM_AVR 83         /* Atmel AVR 8-bit microcontroller */
+#define EM_FR30 84        /* Fujitsu FR30 */
+#define EM_D10V 85        /* Mitsubishi D10V */
+#define EM_D30V 86        /* Mitsubishi D30V */
+#define EM_V850 87        /* Renesas V850 (formerly NEC V850) */
+#define EM_M32R 88        /* Renesas M32R (formerly Mitsubishi M32R) */
+#define EM_MN10300 89     /* Matsushita MN10300 */
+#define EM_MN10200 90     /* Matsushita MN10200 */
+#define EM_PJ 91          /* picoJava */
+#define EM_OR1K 92        /* OpenRISC 1000 32-bit embedded processor */
+#define EM_ARC_COMPACT 93 /* ARC International ARCompact processor */
+#define EM_XTENSA 94      /* Tensilica Xtensa Architecture */
+#define EM_SCORE_OLD                                                           \
+  95 /* Old Sunplus S+core7 backend magic number. Written in the absence of    \
+        an ABI.  */
+#define EM_VIDEOCORE 95 /* Alphamosaic VideoCore processor */
+#define EM_TMM_GPP 96   /* Thompson Multimedia General Purpose Processor */
+#define EM_NS32K 97     /* National Semiconductor 32000 series */
+#define EM_TPC 98       /* Tenor Network TPC processor */
+#define EM_PJ_OLD 99    /* Old value for picoJava.  Deprecated.  */
+#define EM_SNP1K 99     /* Trebia SNP 1000 processor */
+#define EM_ST200 100    /* STMicroelectronics ST200 microcontroller */
+#define EM_IP2K 101     /* Ubicom IP2022 micro controller */
+#define EM_MAX 102      /* MAX Processor */
+#define EM_CR 103       /* National Semiconductor CompactRISC */
+#define EM_F2MC16 104   /* Fujitsu F2MC16 */
+#define EM_MSP430 105   /* TI msp430 micro controller */
+#define EM_BLACKFIN 106 /* ADI Blackfin */
+#define EM_SE_C33 107   /* S1C33 Family of Seiko Epson processors */
+#define EM_SEP 108      /* Sharp embedded microprocessor */
+#define EM_ARCA 109     /* Arca RISC Microprocessor */
+#define EM_UNICORE                                                             \
+  110 /* Microprocessor series from PKU-Unity Ltd. and MPRC of Peking          \
+         University */
+#define EM_EXCESS 111 /* eXcess: 16/32/64-bit configurable embedded CPU */
+#define EM_DXP 112    /* Icera Semiconductor Inc. Deep Execution Processor */
+#define EM_ALTERA_NIOS2 113 /* Altera Nios II soft-core processor */
+#define EM_CRX 114          /* National Semiconductor CRX */
+#define EM_CR16_OLD                                                            \
+  115 /* Old, value for National Semiconductor CompactRISC.  Deprecated.  */
+#define EM_XGATE 115 /* Motorola XGATE embedded processor */
+#define EM_C166 116  /* Infineon C16x/XC16x processor */
+#define EM_M16C 117  /* Renesas M16C series microprocessors */
+#define EM_DSPIC30F                                                            \
+  118             /* Microchip Technology dsPIC30F Digital Signal Controller */
+#define EM_CE 119 /* Freescale Communication Engine RISC core */
+#define EM_M32C 120       /* Renesas M32C series microprocessors */
+#define EM_res121 121     /* Reserved */
+#define EM_res122 122     /* Reserved */
+#define EM_res123 123     /* Reserved */
+#define EM_res124 124     /* Reserved */
+#define EM_res125 125     /* Reserved */
+#define EM_res126 126     /* Reserved */
+#define EM_res127 127     /* Reserved */
+#define EM_res128 128     /* Reserved */
+#define EM_res129 129     /* Reserved */
+#define EM_res130 130     /* Reserved */
+#define EM_TSK3000 131    /* Altium TSK3000 core */
+#define EM_RS08 132       /* Freescale RS08 embedded processor */
+#define EM_res133 133     /* Reserved */
+#define EM_ECOG2 134      /* Cyan Technology eCOG2 microprocessor */
+#define EM_SCORE 135      /* Sunplus Score */
+#define EM_SCORE7 135     /* Sunplus S+core7 RISC processor */
+#define EM_DSP24 136      /* New Japan Radio (NJR) 24-bit DSP Processor */
+#define EM_VIDEOCORE3 137 /* Broadcom VideoCore III processor */
+#define EM_LATTICEMICO32                                                       \
+  138                   /* RISC processor for Lattice FPGA architecture        \
+                         */
+#define EM_SE_C17 139   /* Seiko Epson C17 family */
+#define EM_TI_C6000 140 /* Texas Instruments TMS320C6000 DSP family */
+#define EM_TI_C2000 141 /* Texas Instruments TMS320C2000 DSP family */
+#define EM_TI_C5500 142 /* Texas Instruments TMS320C55x DSP family */
+#define EM_res143 143   /* Reserved */
+#define EM_TI_PRU 144   /* Texas Instruments Programmable Realtime Unit */
+#define EM_res145 145   /* Reserved */
+#define EM_res146 146   /* Reserved */
+#define EM_res147 147   /* Reserved */
+#define EM_res148 148   /* Reserved */
+#define EM_res149 149   /* Reserved */
+#define EM_res150 150   /* Reserved */
+#define EM_res151 151   /* Reserved */
+#define EM_res152 152   /* Reserved */
+#define EM_res153 153   /* Reserved */
+#define EM_res154 154   /* Reserved */
+#define EM_res155 155   /* Reserved */
+#define EM_res156 156   /* Reserved */
+#define EM_res157 157   /* Reserved */
+#define EM_res158 158   /* Reserved */
+#define EM_res159 159   /* Reserved */
+#define EM_MMDSP_PLUS                                                          \
+  160 /* STMicroelectronics 64bit VLIW Data Signal Processor */
+#define EM_CYPRESS_M8C 161 /* Cypress M8C microprocessor */
+#define EM_R32C 162        /* Renesas R32C series microprocessors */
+#define EM_TRIMEDIA 163    /* NXP Semiconductors TriMedia architecture family */
+#define EM_QDSP6 164       /* QUALCOMM DSP6 Processor */
+#define EM_8051 165        /* Intel 8051 and variants */
+#define EM_STXP7X 166      /* STMicroelectronics STxP7x family */
+#define EM_NDS32                                                               \
+  167 /* Andes Technology compact code size embedded RISC processor family */
+#define EM_ECOG1 168  /* Cyan Technology eCOG1X family */
+#define EM_ECOG1X 168 /* Cyan Technology eCOG1X family */
+#define EM_MAXQ30                                                              \
+  169                  /* Dallas Semiconductor MAXQ30 Core Micro-controllers   \
+                        */
+#define EM_XIMO16 170  /* New Japan Radio (NJR) 16-bit DSP Processor */
+#define EM_MANIK 171   /* M2000 Reconfigurable RISC Microprocessor */
+#define EM_CRAYNV2 172 /* Cray Inc. NV2 vector architecture */
+#define EM_RX 173      /* Renesas RX family */
+#define EM_METAG                                                               \
+  174 /* Imagination Technologies Meta processor architecture                  \
+       */
+#define EM_MCST_ELBRUS                                                         \
+  175                 /* MCST Elbrus general purpose hardware architecture */
+#define EM_ECOG16 176 /* Cyan Technology eCOG16 family */
+#define EM_CR16 177   /* National Semiconductor CompactRISC 16-bit processor */
+#define EM_ETPU 178   /* Freescale Extended Time Processing Unit */
+#define EM_SLE9X 179  /* Infineon Technologies SLE9X core */
+#define EM_L1OM 180   /* Intel L1OM */
+#define EM_K1OM 181   /* Intel K1OM */
+#define EM_INTEL182 182 /* Reserved by Intel */
+#define EM_AARCH64 183  /* ARM 64-bit architecture */
+#define EM_ARM184 184   /* Reserved by ARM */
+#define EM_AVR32 185    /* Atmel Corporation 32-bit microprocessor family */
+#define EM_STM8 186     /* STMicroeletronics STM8 8-bit microcontroller */
+#define EM_TILE64 187   /* Tilera TILE64 multicore architecture family */
+#define EM_TILEPRO 188  /* Tilera TILEPro multicore architecture family */
+#define EM_MICROBLAZE                                                          \
+  189                 /* Xilinx MicroBlaze 32-bit RISC soft processor core */
+#define EM_CUDA 190   /* NVIDIA CUDA architecture */
+#define EM_TILEGX 191 /* Tilera TILE-Gx multicore architecture family */
+#define EM_CLOUDSHIELD 192 /* CloudShield architecture family */
+#define EM_COREA_1ST                                                           \
+  193 /* KIPO-KAIST Core-A 1st generation processor family                     \
+       */
+#define EM_COREA_2ND                                                           \
+  194 /* KIPO-KAIST Core-A 2nd generation processor family                     \
+       */
+#define EM_ARC_COMPACT2 195 /* Synopsys ARCompact V2 */
+#define EM_OPEN8 196        /* Open8 8-bit RISC soft processor core */
+#define EM_RL78 197         /* Renesas RL78 family.  */
+#define EM_VIDEOCORE5 198   /* Broadcom VideoCore V processor */
+#define EM_78K0R 199        /* Renesas 78K0R.  */
+#define EM_56800EX                                                             \
+  200                   /* Freescale 56800EX Digital Signal Controller (DSC)   \
+                         */
+#define EM_BA1 201      /* Beyond BA1 CPU architecture */
+#define EM_BA2 202      /* Beyond BA2 CPU architecture */
+#define EM_XCORE 203    /* XMOS xCORE processor family */
+#define EM_MCHP_PIC 204 /* Microchip 8-bit PIC(r) family */
+#define EM_INTEL205 205 /* Reserved by Intel */
+#define EM_INTEL206 206 /* Reserved by Intel */
+#define EM_INTEL207 207 /* Reserved by Intel */
+#define EM_INTEL208 208 /* Reserved by Intel */
+#define EM_INTEL209 209 /* Reserved by Intel */
+#define EM_KM32 210     /* KM211 KM32 32-bit processor */
+#define EM_KMX32 211    /* KM211 KMX32 32-bit processor */
+#define EM_KMX16 212    /* KM211 KMX16 16-bit processor */
+#define EM_KMX8 213     /* KM211 KMX8 8-bit processor */
+#define EM_KVARC 214    /* KM211 KVARC processor */
+#define EM_CDP 215      /* Paneve CDP architecture family */
+#define EM_COGE 216     /* Cognitive Smart Memory Processor */
+#define EM_COOL 217     /* Bluechip Systems CoolEngine */
+#define EM_NORC 218     /* Nanoradio Optimized RISC */
+#define EM_CSR_KALIMBA 219 /* CSR Kalimba architecture family */
+#define EM_Z80 220         /* Zilog Z80 */
+#define EM_VISIUM 221      /* Controls and Data Services VISIUMcore processor */
+#define EM_FT32                                                                \
+  222 /* FTDI Chip FT32 high performance 32-bit RISC architecture */
+#define EM_MOXIE 223  /* Moxie processor family */
+#define EM_AMDGPU 224 /* AMD GPU architecture */
+#define EM_RISCV 243  /* RISC-V */
+#define EM_LANAI 244  /* Lanai 32-bit processor.  */
+#define EM_BPF 247    /* Linux BPF – in-kernel virtual machine.  */
+#define EM_NFP 250    /* Netronome Flow Processor.  */
+#define EM_CSKY 252   /* C-SKY processor family.  */
+
+/* Values of note segment descriptor types for core files.  */
+
+#define NT_PRSTATUS    1        /* Contains copy of prstatus struct */
+#define NT_FPREGSET    2        /* Contains copy of fpregset struct */
+#define NT_PRPSINFO    3        /* Contains copy of prpsinfo struct */
+#define NT_TASKSTRUCT    4        /* Contains copy of task struct */
+#define NT_AUXV        6        /* Contains copy of Elfxx_auxv_t */
+#define NT_PRXFPREG    0x46e62b7f    /* Contains a user_xfpregs_struct; */
+/*   note name must be "LINUX".  */
+#define NT_PPC_VMX    0x100        /* PowerPC Altivec/VMX registers */
+/*   note name must be "LINUX".  */
+#define NT_PPC_VSX    0x102        /* PowerPC VSX registers */
+/*   note name must be "LINUX".  */
+#define NT_PPC_TAR    0x103        /* PowerPC Target Address Register */
+/*   note name must be "LINUX".  */
+#define NT_PPC_PPR    0x104        /* PowerPC Program Priority Register */
+/*   note name must be "LINUX".  */
+#define NT_PPC_DSCR    0x105        /* PowerPC Data Stream Control Register */
+/*   note name must be "LINUX".  */
+#define NT_PPC_EBB    0x106        /* PowerPC Event Based Branch Registers */
+/*   note name must be "LINUX".  */
+#define NT_PPC_PMU    0x107        /* PowerPC Performance Monitor Registers */
+/*   note name must be "LINUX".  */
+#define NT_PPC_TM_CGPR    0x108        /* PowerPC TM checkpointed GPR Registers */
+/*   note name must be "LINUX".  */
+#define NT_PPC_TM_CFPR    0x109        /* PowerPC TM checkpointed FPR Registers */
+/*   note name must be "LINUX".  */
+#define NT_PPC_TM_CVMX    0x10a        /* PowerPC TM checkpointed VMX Registers */
+/*   note name must be "LINUX".  */
+#define NT_PPC_TM_CVSX    0x10b        /* PowerPC TM checkpointed VSX Registers */
+/*   note name must be "LINUX".  */
+#define NT_PPC_TM_SPR    0x10c        /* PowerPC TM Special Purpose Registers */
+/*   note name must be "LINUX".  */
+#define NT_PPC_TM_CTAR    0x10d        /* PowerPC TM checkpointed TAR */
+/*   note name must be "LINUX".  */
+#define NT_PPC_TM_CPPR    0x10e        /* PowerPC TM checkpointed PPR */
+/*   note name must be "LINUX".  */
+#define NT_PPC_TM_CDSCR    0x10f        /* PowerPC TM checkpointed Data SCR */
+/*   note name must be "LINUX".  */
+#define NT_386_TLS    0x200        /* x86 TLS information */
+/*   note name must be "LINUX".  */
+#define NT_386_IOPERM    0x201        /* x86 io permissions */
+/*   note name must be "LINUX".  */
+#define NT_X86_XSTATE    0x202        /* x86 XSAVE extended state */
+/*   note name must be "LINUX".  */
+#define NT_X86_CET    0x203        /* x86 CET state.  */
+/*   note name must be "LINUX".  */
+#define NT_S390_HIGH_GPRS 0x300        /* S/390 upper halves of GPRs  */
+/*   note name must be "LINUX".  */
+#define NT_S390_TIMER    0x301        /* S390 timer */
+/*   note name must be "LINUX".  */
+#define NT_S390_TODCMP    0x302        /* S390 TOD clock comparator */
+/*   note name must be "LINUX".  */
+#define NT_S390_TODPREG    0x303        /* S390 TOD programmable register */
+/*   note name must be "LINUX".  */
+#define NT_S390_CTRS    0x304        /* S390 control registers */
+/*   note name must be "LINUX".  */
+#define NT_S390_PREFIX    0x305        /* S390 prefix register */
+/*   note name must be "LINUX".  */
+#define NT_S390_LAST_BREAK      0x306   /* S390 breaking event address */
+/*   note name must be "LINUX".  */
+#define NT_S390_SYSTEM_CALL     0x307   /* S390 system call restart data */
+/*   note name must be "LINUX".  */
+#define NT_S390_TDB    0x308        /* S390 transaction diagnostic block */
+/*   note name must be "LINUX".  */
+#define NT_S390_VXRS_LOW    0x309    /* S390 vector registers 0-15 upper half */
+/*   note name must be "LINUX".  */
+#define NT_S390_VXRS_HIGH    0x30a    /* S390 vector registers 16-31 */
+/*   note name must be "LINUX".  */
+#define NT_S390_GS_CB    0x30b        /* s390 guarded storage registers */
+/*   note name must be "LINUX".  */
+#define NT_S390_GS_BC    0x30c        /* s390 guarded storage broadcast control block */
+/*   note name must be "LINUX".  */
+#define NT_ARM_VFP    0x400        /* ARM VFP registers */
+/* The following definitions should really use NT_AARCH_..., but defined
+   this way for compatibility with Linux.  */
+#define NT_ARM_TLS    0x401        /* AArch TLS registers */
+/*   note name must be "LINUX".  */
+#define NT_ARM_HW_BREAK    0x402        /* AArch hardware breakpoint registers */
+/*   note name must be "LINUX".  */
+#define NT_ARM_HW_WATCH    0x403        /* AArch hardware watchpoint registers */
+/*   note name must be "LINUX".  */
+#define NT_ARM_SVE    0x405        /* AArch SVE registers.  */
+/*   note name must be "LINUX".  */
+#define NT_ARM_PAC_MASK    0x406        /* AArch pointer authentication code masks */
+/*   note name must be "LINUX".  */
+#define NT_ARC_V2    0x600        /* ARC HS accumulator/extra registers.  */
+/*   note name must be "LINUX".  */
+#define NT_SIGINFO    0x53494749    /* Fields of siginfo_t.  */
+#define NT_FILE        0x46494c45    /* Description of mapped files.  */
+
+/* Values for program header, p_type field.  */
+
+#define PT_NULL        0        /* Program header table entry unused */
+#define PT_LOAD        1        /* Loadable program segment */
+#define PT_DYNAMIC    2        /* Dynamic linking information */
+#define PT_INTERP    3        /* Program interpreter */
+#define PT_NOTE        4        /* Auxiliary information */
+#define PT_SHLIB    5        /* Reserved, unspecified semantics */
+#define PT_PHDR        6        /* Entry for header table itself */
+#define PT_TLS        7        /* Thread local storage segment */
+#define PT_LOOS        0x60000000    /* OS-specific */
+#define PT_HIOS        0x6fffffff    /* OS-specific */
+#define PT_LOPROC    0x70000000    /* Processor-specific */
+#define PT_HIPROC    0x7FFFFFFF    /* Processor-specific */
+
+/* Program segment permissions, in program header p_flags field.  */
+
+#define PF_X        (1 << 0)    /* Segment is executable */
+#define PF_W        (1 << 1)    /* Segment is writable */
+#define PF_R        (1 << 2)    /* Segment is readable */
+/* #define PF_MASKOS    0x0F000000    *//* OS-specific reserved bits */
+#define PF_MASKOS    0x0FF00000    /* New value, Oct 4, 1999 Draft */
+#define PF_MASKPROC    0xF0000000    /* Processor-specific reserved bits */
+
+#define CORE_MEM_LINE_MASK  0xFFFFFFC0
+
+#endif /* __MCD_ELF_DEFINE_H__ */

Middlewares/MCoreDump/osal/rtthread.c

@@ -0,0 +1,238 @@
+/*
+ * Copyright (c) 2025, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2025-08-16     Rbb666       first version
+ */
+
+#include <rtthread.h>
+#include "coredump.h"
+#include "mcd_arch_interface.h"
+
+/*
+ * RT-Thread OS abstraction layer implementation for MCoreDump
+ */
+typedef struct
+{
+    rt_int32_t thr_cnts;
+    rt_int32_t cur_idx;
+} rtthread_ti_priv_t;
+
+/* Architecture-specific exception hook function */
+#ifdef PKG_USING_MCOREDUMP_ARCH_ARMV7M
+#define arch_hard_fault_exception_hook armv7m_hard_fault_exception_hook
+#elif defined(PKG_USING_MCOREDUMP_ARCH_ARMV8M)
+#define arch_hard_fault_exception_hook armv8m_hard_fault_exception_hook
+#else
+#error "MCoredump does not support this architecture"
+#endif
+
+static rt_int32_t is_thread_object(rt_thread_t thread)
+{
+    /* Check if the object is a thread (both static and dynamic) */
+    return ((thread->type & ~RT_Object_Class_Static) == RT_Object_Class_Thread);
+}
+
+static int32_t rtthread_thr_cnts(struct thread_info_ops *ops)
+{
+    rtthread_ti_priv_t *priv = (rtthread_ti_priv_t *)ops->priv;
+    rt_int32_t idx = 0;
+    struct rt_object_information *information;
+    struct rt_object *object;
+    struct rt_list_node *node;
+    rt_thread_t current_thread;
+
+    if (-1 == priv->thr_cnts)
+    {
+        information = rt_object_get_information(RT_Object_Class_Thread);
+        mcd_assert(information != RT_NULL);
+        
+        current_thread = rt_thread_self();
+        priv->cur_idx = -1;  /* Initialize current thread index */
+
+        for (node = information->object_list.next;
+                node != &(information->object_list);
+                node = node->next)
+        {
+            object = rt_list_entry(node, struct rt_object, list);
+            rt_thread_t thread = (rt_thread_t)object;
+
+            if (is_thread_object(thread))
+            {
+                /* Check if this is the current thread */
+                if (thread == current_thread)
+                {
+                    priv->cur_idx = idx;
+                }
+                idx++;
+            }
+        }
+
+        priv->thr_cnts = idx;
+        
+        /* If current thread not found, default to 0 */
+        if (priv->cur_idx == -1)
+        {
+            priv->cur_idx = 0;
+            mcd_print("MCD DEBUG: Current thread not found, defaulting to index 0\n");
+        }
+    }
+
+    return priv->thr_cnts;
+}
+
+static int32_t rtthread_cur_idx(struct thread_info_ops *ops)
+{
+    rtthread_ti_priv_t *priv = (rtthread_ti_priv_t *)ops->priv;
+
+    if (-1 == priv->cur_idx)
+        rtthread_thr_cnts(ops);
+
+    return priv->cur_idx;
+}
+
+static void rtthread_thr_rset(struct thread_info_ops *ops, int32_t idx,
+                              core_regset_type *core_regset,
+                              fp_regset_type *fp_regset)
+{
+    rt_int32_t idx_l = 0;
+    rt_int32_t current_idx = rtthread_cur_idx(ops);
+    struct rt_object_information *information;
+    struct rt_object *object;
+    struct rt_list_node *node;
+
+    information = rt_object_get_information(RT_Object_Class_Thread);
+    mcd_assert(information != RT_NULL);
+
+    for (node = information->object_list.next;
+            node != &(information->object_list);
+            node = node->next)
+    {
+        object = rt_list_entry(node, struct rt_object, list);
+        rt_thread_t thread = (rt_thread_t)object;
+
+        if (is_thread_object(thread))
+        {
+            if (idx == idx_l)
+            {
+                /* If this is the current thread, use current registers */
+                if (idx_l == current_idx)
+                {
+                    mcd_memcpy(core_regset, get_cur_core_regset_address(), sizeof(core_regset_type));
+                    mcd_memcpy(fp_regset, get_cur_fp_regset_address(), sizeof(fp_regset_type));
+                }
+                else
+                {
+                    /* Debug: Dynamic thread for comparison */
+                    collect_registers((uint32_t *)thread->sp, core_regset, fp_regset);
+                }
+                return;
+            }
+            idx_l++;
+        }
+    }
+}
+
+static int32_t rtthread_get_mem_cnts(struct thread_info_ops *ops)
+{
+    return rtthread_thr_cnts(ops);
+}
+
+static int32_t rtthread_get_memarea(struct thread_info_ops *ops, int32_t idx,
+                                       uint32_t *addr, uint32_t *memlen)
+{
+    rt_int32_t         idx_l = 0;
+    rt_int32_t current_idx = rtthread_cur_idx(ops);
+    struct rt_object_information *information;
+    struct rt_object *object;
+    struct rt_list_node *node;
+
+    information = rt_object_get_information(RT_Object_Class_Thread);
+    mcd_assert(information != RT_NULL);
+
+    for (node = information->object_list.next;
+            node != &(information->object_list);
+            node = node->next)
+    {
+        object = rt_list_entry(node, struct rt_object, list);
+        rt_thread_t thread = (rt_thread_t)object;
+
+        if (is_thread_object(thread))
+        {
+            if (idx == idx_l)
+            {
+                /* If this is the current thread, use current stack pointer */
+                if (idx_l == current_idx)
+                {
+                    *addr = get_cur_core_regset_address()->sp;
+                    *memlen = 1024;
+                }
+                else
+                {
+                    *addr = (rt_uint32_t)thread->sp;
+                    *memlen = (rt_uint32_t)thread->stack_addr + thread->stack_size - (rt_uint32_t)thread->sp;
+                }
+                return 0;
+            }
+            idx_l++;
+        }
+    }
+    return 0;
+}
+
+void mcd_rtos_thread_ops(struct thread_info_ops *ops)
+{
+    static rtthread_ti_priv_t priv;
+    ops->get_threads_count = rtthread_thr_cnts;
+    ops->get_current_thread_idx = rtthread_cur_idx;
+    ops->get_thread_regset = rtthread_thr_rset;
+    ops->get_memarea_count = rtthread_get_mem_cnts;
+    ops->get_memarea = rtthread_get_memarea;
+    ops->priv = &priv;
+    priv.cur_idx = -1;
+    priv.thr_cnts = -1;
+}
+
+MCD_WEAK rt_err_t rtt_hard_fault_exception_hook(void *context)
+{
+    arch_hard_fault_exception_hook(context);
+    return -RT_ERROR;
+}
+
+MCD_WEAK void rtt_assert_hook(const char *ex, const char *func, rt_size_t line)
+{
+    volatile uint8_t _continue = 1;
+
+    rt_interrupt_enter();
+
+    mcd_print("(%s) has assert failed at %s:%ld.\n", ex, func, line);
+
+    mcd_faultdump(MCD_OUTPUT_SERIAL);
+
+    rt_interrupt_leave();
+
+    while (_continue == 1);
+}
+
+static int mcd_coredump_init(void) 
+{
+    static mcd_bool_t is_init = MCD_FALSE;
+
+    if (is_init)
+    {
+        return 0;
+    }
+
+    //mcd_print_memoryinfo();
+    
+    rt_hw_exception_install(rtt_hard_fault_exception_hook);
+
+    //rt_assert_set_hook(rtt_assert_hook);
+    
+    is_init = MCD_TRUE;
+    return RT_EOK;
+}
+INIT_DEVICE_EXPORT(mcd_coredump_init);

Middlewares/MCoreDump/src/arm/mcd_arm.c

@@ -0,0 +1,102 @@
+/*
+ * Copyright (c) 2025, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2025-08-16     Rbb666       Unified ARM architecture implementation
+ */
+
+#include <stdint.h>
+#include "mcd_cfg.h"
+#include "mcd_arm_define.h"
+
+/* Global task ID counter for note generation */
+static uint32_t task_id_counter = 3539;
+
+#if MCD_ARM_ARCH_32BIT
+/**
+ * @brief Fill prstatus note description for ARM32
+ * 
+ * @param desc Pointer to description buffer
+ * @param regset Pointer to core register set
+ */
+void arm32_fill_note_prstatus_desc(uint8_t *desc, core_regset_type *regset)
+{
+    uint16_t *signal = (uint16_t *)&desc[12];
+    uint32_t *lwpid = (uint32_t *)&desc[24];
+
+    mcd_memset(desc, 0, MCOREDUMP_PRSTATUS_SIZE);
+    *signal = 0;
+    *lwpid = task_id_counter++;
+    
+    /* Copy ARM32 registers to offset 72 */
+    mcd_memcpy(desc + MCD_PRSTATUS_REG_OFFSET, regset, sizeof(core_regset_type));
+}
+
+/**
+ * @brief Fill fpregset note description for ARM32
+ * 
+ * @param desc Pointer to description buffer
+ * @param regset Pointer to floating point register set
+ */
+void arm32_fill_note_fpregset_desc(uint8_t *desc, fp_regset_type *regset)
+{
+    if (regset != 0)
+    {
+        /* Copy VFP registers (32 * 8 bytes = 256 bytes) */
+        mcd_memcpy(desc, regset, sizeof(fp_regset_type) - sizeof(uint32_t));
+        /* Copy FPSCR at the end */
+        mcd_memcpy(desc + 32 * 8, &regset->fpscr, sizeof(uint32_t));
+    }
+    else
+    {
+        mcd_memset(desc, 0, MCOREDUMP_FPREGSET_SIZE);
+    }
+}
+#endif /* MCD_ARM_ARCH_32BIT */
+
+#if MCD_ARM_ARCH_64BIT
+/**
+ * @brief Fill prstatus note description for ARM64
+ * 
+ * @param desc Pointer to description buffer
+ * @param regset Pointer to core register set
+ */
+void arm64_fill_note_prstatus_desc(uint8_t *desc, core_regset_type *regset)
+{
+    uint16_t *signal = (uint16_t *)&desc[12];
+    uint32_t *lwpid = (uint32_t *)&desc[32];
+
+    mcd_memset(desc, 0, MCOREDUMP_PRSTATUS_SIZE);
+    *signal = 0;
+    *lwpid = task_id_counter++;
+    
+    /* Copy ARM64 registers to offset 112 */
+    mcd_memcpy(desc + MCD_PRSTATUS_REG_OFFSET, regset, sizeof(core_regset_type));
+}
+
+/**
+ * @brief Fill fpregset note description for ARM64
+ * 
+ * @param desc Pointer to description buffer  
+ * @param regset Pointer to floating point register set
+ */
+void arm64_fill_note_fpregset_desc(uint8_t *desc, fp_regset_type *regset)
+{
+    if (regset != NULL)
+    {
+        /* Copy SIMD/FP registers (32 * 16 bytes = 512 bytes) */
+        mcd_memcpy(desc, regset, sizeof(fp_regset_type) - 8);
+        
+        /* Copy FPSR and FPCR at the end */
+        mcd_memcpy(desc + 32 * 16, &regset->fpsr, sizeof(uint32_t));
+        mcd_memcpy(desc + 32 * 16 + 4, &regset->fpcr, sizeof(uint32_t));
+    }
+    else
+    {
+        mcd_memset(desc, 0, MCOREDUMP_FPREGSET_SIZE);
+    }
+}
+#endif /* MCD_ARM_ARCH_64BIT */

Middlewares/MCoreDump/src/arm/mcd_arm_define.h

@@ -0,0 +1,68 @@
+/*
+ * Copyright (c) 2025, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2025-08-16     Rbb666       Unified ARM architecture definitions
+ */
+
+#ifndef __MCD_ARM_DEFINE_H__
+#define __MCD_ARM_DEFINE_H__
+
+#include "registers.h"
+
+/* ARM Architecture Detection */
+#if defined(__aarch64__) || defined(_M_ARM64)
+#define MCD_ARM_ARCH_64BIT          1
+#define MCD_ARM_ARCH_32BIT          0
+#elif defined(__arm__) || defined(_M_ARM) || defined(__ARM_ARCH)
+#define MCD_ARM_ARCH_64BIT          0
+#define MCD_ARM_ARCH_32BIT          1
+#else
+#error "Unsupported ARM architecture"
+#endif
+
+/* Architecture-specific ELF definitions */
+#if MCD_ARM_ARCH_64BIT
+/* ARM64 (AArch64) definitions */
+#define MCOREDUMP_ELF_CLASS         ELFCLASS64
+#define MCOREDUMP_ELF_ENDIAN        ELFDATA2LSB
+#define MCOREDUMP_MACHINE           EM_AARCH64
+#define MCOREDUMP_OSABI             ELFOSABI_NONE
+#define MCOREDUMP_PRSTATUS_SIZE     392
+#define MCOREDUMP_FPREGSET_SIZE     (32 * 16 + 8)
+#define MCD_PRSTATUS_REG_OFFSET     112
+
+/* Function mappings */
+#define fill_note_prstatus_desc     arm64_fill_note_prstatus_desc
+#define fill_note_fpregset_desc     arm64_fill_note_fpregset_desc
+    
+#elif MCD_ARM_ARCH_32BIT
+/* ARM32 (AArch32) definitions */
+#define MCOREDUMP_ELF_CLASS         ELFCLASS32
+#define MCOREDUMP_ELF_ENDIAN        ELFDATA2LSB
+#define MCOREDUMP_MACHINE           EM_ARM
+#define MCOREDUMP_OSABI             ELFOSABI_ARM
+#define MCOREDUMP_PRSTATUS_SIZE     148
+#define MCOREDUMP_FPREGSET_SIZE     (32 * 8 + 4)
+#define MCD_PRSTATUS_REG_OFFSET     72
+
+/* Function mappings */
+#define fill_note_prstatus_desc     arm32_fill_note_prstatus_desc
+#define fill_note_fpregset_desc     arm32_fill_note_fpregset_desc
+#endif /* MCD_ARM_ARCH_32BIT */
+
+/* Function declarations */
+#if MCD_ARM_ARCH_32BIT
+void arm32_fill_note_prstatus_desc(uint8_t *desc, core_regset_type *regset);
+void arm32_fill_note_fpregset_desc(uint8_t *desc, fp_regset_type *regset);
+#endif
+
+#if MCD_ARM_ARCH_64BIT
+void arm64_fill_note_prstatus_desc(uint8_t *desc, core_regset_type *regset);
+void arm64_fill_note_fpregset_desc(uint8_t *desc, fp_regset_type *regset);
+#endif
+
+#endif /* __MCD_ARM_DEFINE_H__ */

Middlewares/MCoreDump/src/coredump.c

@@ -0,0 +1,355 @@
+/*
+ * Copyright (c) 2025, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2025-08-16     Rbb666       first version
+ */
+
+#include <string.h>
+#include "coredump.h"
+#include "mcd_elf_define.h"
+#include "mcd_arm_define.h"
+
+typedef uint16_t elf_half;
+typedef uint32_t elf_word;
+
+#if MCOREDUMP_ELF_CLASS == ELFCLASS32
+typedef uint32_t elf_addr;
+typedef uint32_t elf_off;
+typedef struct elf32_phdr elf_phdr_t;
+#else
+typedef uint64_t elf_addr;
+typedef uint64_t elf_off;
+typedef struct elf64_phdr elf_phdr_t;
+#endif
+
+/* Elf file header type */
+typedef struct
+{
+    unsigned char e_ident[EI_NIDENT];
+    elf_half e_type;
+    elf_half e_machine;
+    elf_word e_version;
+    elf_addr e_entry;
+    elf_off e_phoff;
+    elf_off e_shoff;
+    elf_word e_flags;
+    elf_half e_ehsize;
+    elf_half e_phentsize;
+    elf_half e_phnum;
+    elf_half e_shentsize;
+    elf_half e_shnum;
+    elf_half e_shstrndx;
+} elf_ehdr_t;
+
+/* Segment header type for 32bit arch */
+struct elf32_phdr
+{
+    elf_word p_type;
+    elf_off p_offset;
+    elf_addr p_vaddr;
+    elf_addr p_paddr;
+    elf_off p_filesz;
+    elf_off p_memsz;
+    elf_word p_flags;
+    elf_off p_align;
+};
+
+/* Segment header type for 64bit arch */
+struct elf64_phdr
+{
+    elf_word p_type;  /* Identifies program segment type */
+    elf_word p_flags; /* Segment flags */
+    elf_off p_offset; /* Segment file offset */
+    elf_addr p_vaddr; /* Segment virtual address */
+    elf_addr p_paddr; /* Segment physical address */
+    elf_off p_filesz; /* Segment size in file */
+    elf_off p_memsz;  /* Segment size in memory */
+    elf_off p_align;  /* Segment alignment, file & memory */
+};
+
+typedef struct
+{
+    elf_word namesz;                       /* Size of entry's owner string */
+    elf_word descsz;                       /* Size of the note descriptor */
+    elf_word type;                         /* Interpretation of the descriptor */
+    char name[1];
+} elf_note_base_t;
+
+typedef struct
+{
+    elf_word namesz;                       /* Size of entry's owner string */
+    elf_word descsz;                       /* Size of the note descriptor */
+    elf_word type;                         /* Interpretation of the descriptor */
+    char name[MCD_ALIGN(sizeof("CORE"), 4)]; /* The only support name is "CORE" */
+    uint8_t desc[MCOREDUMP_PRSTATUS_SIZE];    /* descriptor of this note entry type */
+} elf_note_prstatus_t;
+
+typedef struct
+{
+    elf_word namesz;                        /* Size of entry's owner string */
+    elf_word descsz;                        /* Size of the note descriptor */
+    elf_word type;                          /* Interpretation of the descriptor */
+    char name[MCD_ALIGN(sizeof("LINUX"), 4)]; /* The only support name is "LINUX" */
+    uint8_t desc[MCOREDUMP_FPREGSET_SIZE];     /* descriptor of this note entry type */
+} elf_note_fpreg_entry_t;
+
+typedef struct
+{
+    elf_off file_off;
+    uint32_t with_fp;
+    uint32_t stack_size;
+    mcd_writeout_func_t writeout_func;
+    union
+    {
+        elf_ehdr_t elf_header;
+        elf_phdr_t program_header;
+        elf_note_prstatus_t prstatus;
+        elf_note_fpreg_entry_t note_fp;
+    } tmp;
+    core_regset_type tmp_core_rset;
+    fp_regset_type tmp_fp_rset;
+} mcd_instance_t;
+
+static core_regset_type current_core_regset;
+static fp_regset_type current_fp_regset;
+
+static mcd_instance_t m_ctx;
+
+static void fill_core_file_header(elf_ehdr_t *elf_header, uint16_t num)
+{
+    memset(elf_header, 0, sizeof(elf_ehdr_t));
+
+    elf_header->e_ident[EI_MAG0] = ELFMAG0;
+    elf_header->e_ident[EI_MAG1] = ELFMAG1;
+    elf_header->e_ident[EI_MAG2] = ELFMAG2;
+    elf_header->e_ident[EI_MAG3] = ELFMAG3;
+    elf_header->e_ident[EI_CLASS] = MCOREDUMP_ELF_CLASS;
+    elf_header->e_ident[EI_DATA] = MCOREDUMP_ELF_ENDIAN;
+    elf_header->e_ident[EI_VERSION] = 1;
+    elf_header->e_ident[EI_OSABI] = MCOREDUMP_OSABI;
+    elf_header->e_type = ET_CORE;
+    elf_header->e_machine = MCOREDUMP_MACHINE;
+    elf_header->e_version = 1;
+    elf_header->e_entry = 0;
+    elf_header->e_phoff = sizeof(elf_ehdr_t);
+    elf_header->e_shoff = 0;
+    elf_header->e_flags = 0;
+    elf_header->e_ehsize = sizeof(elf_ehdr_t);
+    elf_header->e_phentsize = sizeof(elf_phdr_t);
+    elf_header->e_phnum = num;
+    elf_header->e_shentsize = 0;
+    elf_header->e_shnum = 0;
+    elf_header->e_shstrndx = 0;
+}
+
+static void fill_program_header(elf_phdr_t *program_header, elf_word type,
+                                elf_addr vaddr, elf_off filesz, elf_off memsz,
+                                elf_word flag)
+{
+    program_header->p_type = type;
+    program_header->p_offset = m_ctx.file_off;
+    program_header->p_vaddr = vaddr;
+    program_header->p_paddr = 0;
+    program_header->p_filesz = filesz;
+    program_header->p_memsz = memsz;
+    program_header->p_flags = flag;
+    program_header->p_align = 1;
+
+    m_ctx.file_off += filesz;
+}
+
+static void fill_note_base(elf_note_base_t *note, const char *note_name,
+                           elf_word type, elf_word descsz)
+{
+    note->namesz = strlen(note_name) + 1;
+    note->descsz = descsz;
+    note->type = type;
+    mcd_memcpy(note->name, note_name, note->namesz);
+    if (note->namesz & 3)
+        memset(&note->name[note->namesz], 0, note->namesz & 3);
+}
+
+/*  fill prstatus struct in note segment */
+static void fill_note_prstatus(elf_note_prstatus_t *prstatus, core_regset_type *regset)
+{
+    fill_note_base((elf_note_base_t *)prstatus, "CORE", NT_PRSTATUS, sizeof(prstatus->desc));
+    fill_note_prstatus_desc(&prstatus->desc[0], regset);
+}
+
+/*  fill FP registers struct in note segment */
+static void fill_note_vfp_regset(elf_note_fpreg_entry_t *prstatus, fp_regset_type *regset)
+{
+    fill_note_base((elf_note_base_t *)prstatus, "LINUX", NT_ARM_VFP, sizeof(prstatus->desc));
+    fill_note_fpregset_desc(&prstatus->desc[0], regset);
+}
+
+void mcd_init(mcd_writeout_func_t func)
+{
+    memset(&m_ctx, 0, sizeof(mcd_instance_t));
+    m_ctx.stack_size = 1536;
+    m_ctx.writeout_func = func;
+    
+    /* Automatically detect FPU support based on compiler definitions */
+    m_ctx.with_fp = MCD_FPU_SUPPORT;
+}
+
+static void fill_one_threads_regset(core_regset_type *core_regset, fp_regset_type *fp_regset)
+{
+    fill_note_prstatus(&m_ctx.tmp.prstatus, core_regset);
+    m_ctx.writeout_func((uint8_t *)&m_ctx.tmp.prstatus, sizeof(elf_note_prstatus_t));
+
+    if (m_ctx.with_fp)
+    {
+        fill_note_vfp_regset(&m_ctx.tmp.note_fp, fp_regset);
+        m_ctx.writeout_func((uint8_t *)&m_ctx.tmp.note_fp, sizeof(elf_note_fpreg_entry_t));
+    }
+}
+
+static void addr_align(uint32_t *addr, uint32_t *memlen)
+{
+    *memlen += ((*addr) & (~CORE_MEM_LINE_MASK));
+    *addr &= CORE_MEM_LINE_MASK;
+}
+
+void mcd_gen_coredump(struct thread_info_ops *ops)
+{
+    int note_size;
+    uint32_t addr, memlen;
+
+    int segment_count = ops->get_memarea_count(ops) + 1;
+    fill_core_file_header(&m_ctx.tmp.elf_header, segment_count);
+    m_ctx.writeout_func((uint8_t *)&m_ctx.tmp.elf_header, sizeof(elf_ehdr_t));
+
+    m_ctx.file_off = sizeof(elf_ehdr_t) + segment_count * sizeof(elf_phdr_t);
+
+    if (m_ctx.with_fp)
+        note_size = (sizeof(elf_note_prstatus_t)
+                     + sizeof(elf_note_fpreg_entry_t))
+                    * ops->get_threads_count(ops);
+    else
+        note_size = sizeof(elf_note_prstatus_t)
+                    * ops->get_threads_count(ops);
+    fill_program_header(&m_ctx.tmp.program_header, PT_NOTE, 0, note_size, 0, PF_R);
+    m_ctx.writeout_func((uint8_t *)&m_ctx.tmp.program_header, sizeof(elf_phdr_t));
+
+    for (int i = 0; i < ops->get_memarea_count(ops); i++)
+    {
+        ops->get_memarea(ops, i, &addr, &memlen);
+        addr_align(&addr, &memlen);
+        fill_program_header(&m_ctx.tmp.program_header, PT_LOAD, addr,
+                            memlen, memlen,
+                            PF_R | PF_W);
+        m_ctx.writeout_func((uint8_t *)&m_ctx.tmp.program_header, sizeof(elf_phdr_t));
+    }
+
+    /* Write all threads in index order */
+    for (int i = 0; i < ops->get_threads_count(ops); i++)
+    {
+        ops->get_thread_regset(ops, i,
+                               &m_ctx.tmp_core_rset, &m_ctx.tmp_fp_rset);
+        fill_one_threads_regset(&m_ctx.tmp_core_rset, &m_ctx.tmp_fp_rset);
+    }
+
+    for (int i = 0; i < ops->get_memarea_count(ops); i++)
+    {
+        ops->get_memarea(ops, i, &addr, &memlen);
+        addr_align(&addr, &memlen);
+        m_ctx.writeout_func((uint8_t *)addr, memlen);
+    }
+}
+
+int32_t mcd_corefile_size(struct thread_info_ops *ops)
+{
+    int elf_size = 0;
+    int segment_count;
+    uint32_t addr, memlen;
+
+    segment_count = ops->get_memarea_count(ops) + 1;
+    elf_size = sizeof(elf_ehdr_t) + segment_count * sizeof(elf_phdr_t);
+
+    if (m_ctx.with_fp)
+        elf_size += (sizeof(elf_note_prstatus_t)
+                     + sizeof(elf_note_fpreg_entry_t))
+                    * ops->get_threads_count(ops);
+    else
+        elf_size += sizeof(elf_note_prstatus_t)
+                    * ops->get_threads_count(ops);
+
+    for (int i = 0; i < ops->get_memarea_count(ops); i++)
+    {
+        ops->get_memarea(ops, i, &addr, &memlen);
+        addr_align(&addr, &memlen);
+        elf_size += memlen;
+    }
+
+    return elf_size;
+}
+
+int32_t mcd_mini_dump_size(void)
+{
+    struct thread_info_ops ops;
+    mcd_mini_dump_ops(&ops);
+    return mcd_corefile_size(&ops);
+}
+
+int32_t mcd_multi_dump_size(void)
+{
+    struct thread_info_ops ops;
+    mcd_rtos_thread_ops(&ops);
+    return mcd_corefile_size(&ops);
+}
+
+static int32_t minidump_thr_cnts(struct thread_info_ops *ops)
+{
+    return 1;
+}
+
+static int32_t minidump_cur_idx(struct thread_info_ops *ops)
+{
+    return 0;
+}
+
+static void minidump_thr_rset(struct thread_info_ops *ops, int32_t idx,
+                              core_regset_type *core_regset,
+                              fp_regset_type *fp_regset)
+{
+    mcd_memcpy(core_regset, get_cur_core_regset_address(), sizeof(core_regset_type));
+    mcd_memcpy(fp_regset, get_cur_fp_regset_address(), sizeof(fp_regset_type));
+}
+
+static int32_t minidump_mem_cnts(struct thread_info_ops *ops)
+{
+    return 1;
+}
+
+static int32_t minidump_memarea(struct thread_info_ops *ops, int32_t idx,
+                                uint32_t *addr, uint32_t *memlen)
+{
+    *addr = current_core_regset.sp;
+    *memlen = m_ctx.stack_size;
+    return 0;
+}
+
+void mcd_mini_dump_ops(struct thread_info_ops *ops)
+{
+    ops->get_threads_count = minidump_thr_cnts;
+    ops->get_current_thread_idx = minidump_cur_idx;
+    ops->get_thread_regset = minidump_thr_rset;
+    ops->get_memarea_count = minidump_mem_cnts;
+    ops->get_memarea = minidump_memarea;
+    ops->priv = NULL;
+}
+
+core_regset_type *get_cur_core_regset_address(void)
+{
+    return &current_core_regset;
+}
+
+fp_regset_type *get_cur_fp_regset_address(void)
+{
+    return &current_fp_regset;
+}

Middlewares/MCoreDump/src/faultdump.c

@@ -0,0 +1,492 @@
+/*
+ * Copyright (c) 2025, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2025-08-16     Rbb666       first version
+ */
+
+#include <stdbool.h>
+#include <stdint.h>
+#include <rtconfig.h>
+#ifdef PKG_USING_MCOREDUMP_FILESYSTEM
+#include <dfs_file.h>
+#include <unistd.h>
+#include <sys/time.h>
+#endif /* PKG_USING_MCOREDUMP_FILESYSTEM */
+#include "coredump.h"
+
+#define COREDUMP_MEMORY_MAGIC       (0x434D4450)  /* "CMDP" */
+
+/* Static memory buffer for coredump storage */
+#ifndef PKG_MCOREDUMP_MEMORY_SIZE
+#define COREDUMP_MEMORY_SIZE        (8 * 1024)    /* Default 8KB buffer size */
+#else
+#define COREDUMP_MEMORY_SIZE        PKG_MCOREDUMP_MEMORY_SIZE
+#endif
+
+typedef struct
+{
+    uint32_t magic;                     /* Magic number to identify valid coredump */
+    uint32_t data_size;                 /* Actual coredump data size */
+    uint32_t crc32;                     /* CRC32 checksum */
+    uint8_t data[COREDUMP_MEMORY_SIZE]; /* Coredump data buffer */
+} coredump_memory_t;
+
+/* Static memory buffer for coredump storage - must persist across resets */
+#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
+/* ARM Compiler V6 (armclang) - use custom section with UNINIT attribute in scatter file */
+static coredump_memory_t coredump_memory_buffer __attribute__((section(".bss.NoInit")));
+#elif defined(__GNUC__)
+/* GCC - use .noinit section (not initialized by startup code) */
+static coredump_memory_t coredump_memory_buffer __attribute__((section(".noinit")));
+#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 6010050)
+/* ARM Compiler 5 (armcc) - use custom section */
+static coredump_memory_t coredump_memory_buffer __attribute__((section(".bss.NoInit"), zero_init));
+#else
+/* Fallback for other compilers - normal static allocation */
+#warning "MCoreDump: Unknown compiler, coredump buffer may not persist across resets"
+#warning "MCoreDump: Data will be lost after system reset"
+static coredump_memory_t coredump_memory_buffer;
+#endif
+
+/* Memory write context */
+static struct
+{
+    uint32_t offset;
+    bool overflow;
+} memory_write_ctx;
+
+#ifdef PKG_USING_MCOREDUMP_FILESYSTEM
+/* Internal function declarations */
+static int create_coredump_filename(void);
+static int prepare_coredump_filesystem(void);
+#endif /* PKG_USING_MCOREDUMP_FILESYSTEM */
+
+/* Global variables for serial output */
+static uint32_t serial_crc32;
+static uint32_t serial_byte_count;
+
+#ifdef PKG_USING_MCOREDUMP_FILESYSTEM
+/* Global variables for filesystem output */
+static int coredump_fd = -1;
+static char coredump_filename[64];
+
+#ifndef PKG_MCOREDUMP_FILESYSTEM_DIR
+#define COREDUMP_DIR "/sdcard"
+#else
+#define COREDUMP_DIR PKG_MCOREDUMP_FILESYSTEM_DIR
+#endif
+
+#ifndef PKG_MCOREDUMP_FILESYSTEM_PREFIX
+#define COREDUMP_PREFIX "core_"
+#else
+#define COREDUMP_PREFIX PKG_MCOREDUMP_FILESYSTEM_PREFIX
+#endif
+
+#define COREDUMP_EXT ".elf"
+#endif /* PKG_USING_MCOREDUMP_FILESYSTEM */
+
+typedef struct
+{
+    uint16_t magic;
+    uint16_t page_size;
+    uint32_t file_size;
+    uint8_t corefile[1];
+} persistent_format_t;
+
+static uint32_t mcd_crc32b(const uint8_t *message, int32_t megLen, uint32_t initCrc)
+{
+    int i, j;
+    uint32_t byte, crc, mask;
+
+    i = 0;
+    crc = initCrc;
+    for (i = 0; i < megLen; i++)
+    {
+        byte = message[i];            /* Get next byte. */
+        crc = crc ^ byte;
+        for (j = 7; j >= 0; j--)      /* Do eight times. */
+        {
+            mask = -(crc & 1);
+            crc = (crc >> 1) ^ (0xEDB88320 & mask);
+        }
+    }
+
+    return ~crc;
+}
+
+static void corefile_serial_write(uint8_t *data, int len)
+{
+    for (int i = 0; i < len; i++)
+    {
+        uint8_t b = data[i];
+        serial_crc32 = mcd_crc32b(&b, 1, serial_crc32) ^ 0xFFFFFFFF;
+        mcd_print("%02x", b);
+        serial_byte_count++;
+    }
+}
+
+static void corefile_memory_write(uint8_t *data, int len)
+{
+    if (memory_write_ctx.overflow)
+        return;
+
+    /* Check if we have enough space */
+    if (memory_write_ctx.offset + len > COREDUMP_MEMORY_SIZE)
+    {
+        memory_write_ctx.overflow = true;
+        mcd_println("WARNING: Coredump memory buffer overflow! Data truncated.");
+        len = COREDUMP_MEMORY_SIZE - memory_write_ctx.offset;
+        if (len <= 0)
+            return;
+    }
+
+    /* Copy data to memory buffer */
+    mcd_memcpy(&coredump_memory_buffer.data[memory_write_ctx.offset], data, len);
+    memory_write_ctx.offset += len;
+}
+
+/**
+ * @brief Check if there's a valid coredump in memory buffer
+ *
+ * @return bool true if valid coredump exists, false otherwise
+ */
+mcd_bool_t mcd_check_memory_coredump(void)
+{
+    return (coredump_memory_buffer.magic == COREDUMP_MEMORY_MAGIC &&
+            coredump_memory_buffer.data_size > 0 &&
+            coredump_memory_buffer.data_size <= COREDUMP_MEMORY_SIZE);
+}
+
+/**
+ * @brief Print coredump memory information at startup
+ *
+ * This function should be called during system initialization
+ */
+void mcd_print_memoryinfo(void)
+{
+    mcd_print("\n=== MCoreDump Memory Check ===\n");
+    mcd_print("Memory buffer address: 0x%08X\n", (uint32_t)&coredump_memory_buffer);
+    mcd_print("Buffer size: %d bytes\n", sizeof(coredump_memory_t));
+
+    if (mcd_check_memory_coredump())
+    {
+        mcd_print("*** COREDUMP FOUND IN MEMORY ***\n");
+        mcd_print("Data size: %d bytes\n", coredump_memory_buffer.data_size);
+#ifdef PKG_USING_MCOREDUMP_FILESYSTEM
+        mcd_print("Use 'mcd_dump_filesystem' command to save to filesystem.\n");
+#endif /* PKG_USING_MCOREDUMP_FILESYSTEM */
+        mcd_print("Use 'mcd_dump_memory' command to dump memory to terminal.\n");
+    }
+    else
+    {
+        mcd_print("No valid coredump found in memory.\n");
+    }
+    mcd_print("============================\n\n");
+}
+
+#ifdef PKG_USING_MCOREDUMP_FILESYSTEM
+/**
+ * @brief Save coredump from memory buffer to filesystem
+ *
+ * @return int MCD_OK on success, error code on failure
+ */
+int mcd_dump_filesystem(void)
+{
+    if (!mcd_check_memory_coredump())
+    {
+        mcd_print("No valid coredump found in memory buffer.\n");
+        return MCD_ERROR;
+    }
+
+    /* Verify CRC32 */
+    uint32_t calculated_crc = mcd_crc32b(coredump_memory_buffer.data,
+                                         coredump_memory_buffer.data_size,
+                                         0xFFFFFFFF) ^ 0xFFFFFFFF;
+
+    if (calculated_crc != coredump_memory_buffer.crc32)
+    {
+        mcd_print("ERROR: Coredump data corruption detected (CRC mismatch)!\n");
+        mcd_print("Expected: 0x%08X, Calculated: 0x%08X\n",
+                   coredump_memory_buffer.crc32, calculated_crc);
+        return MCD_ERROR;
+    }
+
+    /* Prepare filesystem */
+    if (prepare_coredump_filesystem() != 0)
+    {
+        mcd_print("ERROR: Failed to prepare filesystem for coredump\n");
+        return MCD_ERROR;
+    }
+
+    mcd_print("Saving coredump from memory to file: %s\n", coredump_filename);
+
+    /* Write coredump data directly (pure ELF format without custom header) */
+    if (write(coredump_fd, coredump_memory_buffer.data, coredump_memory_buffer.data_size) < 0)
+    {
+        mcd_print("ERROR: Failed to write coredump data\n");
+        close(coredump_fd);
+        return MCD_ERROR;
+    }
+
+    close(coredump_fd);
+    coredump_fd = -1;
+
+    mcd_print("Coredump saved successfully to: %s\n", coredump_filename);
+
+    /* Clear memory buffer after successful save */
+    mcd_memset(&coredump_memory_buffer, 0, sizeof(coredump_memory_t));
+
+    return MCD_OK;
+}
+MCD_CMD_EXPORT(mcd_dump_filesystem, Save coredump from memory to filesystem);
+
+static int create_coredump_filename(void)
+{
+    struct timeval tv;
+    struct tm *tm_info;
+
+    /* Get current time */
+    if (gettimeofday(&tv, NULL) != 0)
+    {
+        /* If time is not available, use a simple counter-based name */
+        static int file_counter = 0;
+        file_counter++;
+        snprintf(coredump_filename, sizeof(coredump_filename),
+                 "%s/%s%04d%s",
+                 COREDUMP_DIR, COREDUMP_PREFIX, file_counter, COREDUMP_EXT);
+    }
+    else
+    {
+        tm_info = localtime(&tv.tv_sec);
+
+        /* Create filename with timestamp */
+        snprintf(coredump_filename, sizeof(coredump_filename),
+                 "%s/%s%04d%02d%02d_%02d%02d%02d%s",
+                 COREDUMP_DIR, COREDUMP_PREFIX,
+                 tm_info->tm_year + 1900, tm_info->tm_mon + 1, tm_info->tm_mday,
+                 tm_info->tm_hour, tm_info->tm_min, tm_info->tm_sec,
+                 COREDUMP_EXT);
+    }
+
+    return 0;
+}
+
+static int prepare_coredump_filesystem(void)
+{
+    struct stat st;
+
+    /* Check if coredump directory exists first */
+    if (stat(COREDUMP_DIR, &st) != 0)
+    {
+        mcd_print("ERROR: %s directory not found. Please mount filesystem first.\n", COREDUMP_DIR);
+        return -1;
+    }
+
+    /* Create coredump directory if it doesn't exist */
+    if (stat(COREDUMP_DIR, &st) != 0)
+    {
+        mcd_print("Creating directory: %s\n", COREDUMP_DIR);
+        if (mkdir(COREDUMP_DIR, 0x777) != 0)
+        {
+            mcd_print("ERROR: Failed to create coredump directory: %s\n", COREDUMP_DIR);
+            mcd_print("Please check if filesystem is mounted and writable.\n");
+            return -1;
+        }
+        mcd_print("Directory created successfully: %s\n", COREDUMP_DIR);
+    }
+
+    /* Generate filename */
+    create_coredump_filename();
+
+    mcd_print("Creating coredump file: %s\n", coredump_filename);
+
+    /* Open file for writing */
+    coredump_fd = open(coredump_filename, O_WRONLY | O_CREAT);
+    if (coredump_fd < 0)
+    {
+        mcd_print("ERROR: Failed to create coredump file: %s\n", coredump_filename);
+        return -1;
+    }
+
+    mcd_print("Coredump file opened successfully (fd: %d)\n", coredump_fd);
+    return 0;
+}
+#endif /* PKG_USING_MCOREDUMP_FILESYSTEM */
+
+/**
+ * @brief Core dump with output mode selection
+ *
+ * @param output_mode MCD_OUTPUT_FLASH for flash storage, MCD_OUTPUT_SERIAL for serial output, MCD_OUTPUT_MEMORY for memory storage
+ * @return int MCD_OK on success, error code on failure
+ */
+int mcd_faultdump_ex(mcd_output_mode_t output_mode)
+{
+    struct thread_info_ops ops;
+
+    if (output_mode == MCD_OUTPUT_SERIAL)
+    {
+        mcd_init(corefile_serial_write);
+
+        mcd_irq_state_t irq_save = mcd_irq_disable();
+
+        serial_crc32 = 0xFFFFFFFF;
+
+        mcd_print("coredump start : {\n");
+        mcd_multi_dump();
+        mcd_print("\n} coredump end\n");
+
+        serial_crc32 = ~serial_crc32;
+
+        mcd_print("crc32 : %08x\n", serial_crc32);
+
+        mcd_irq_enable(irq_save);
+    }
+    else if (output_mode == MCD_OUTPUT_MEMORY)
+    {
+        /* Memory buffer output mode - for exception handling */
+        mcd_print("\n=== MCoreDump Memory Storage Started ===\n");
+
+        /* Initialize memory write context */
+        memory_write_ctx.offset = 0;
+        memory_write_ctx.overflow = false;
+
+        /* Clear memory buffer */
+        mcd_memset(&coredump_memory_buffer, 0, sizeof(coredump_memory_t));
+
+        /* Initialize mcd with memory write function */
+        mcd_init(corefile_memory_write);
+
+        /* Generate and write coredump to memory */
+        mcd_rtos_thread_ops(&ops);
+        mcd_gen_coredump(&ops);
+
+        /* Finalize memory buffer */
+        if (!memory_write_ctx.overflow && memory_write_ctx.offset > 0)
+        {
+            coredump_memory_buffer.magic = COREDUMP_MEMORY_MAGIC;
+            coredump_memory_buffer.data_size = memory_write_ctx.offset;
+            coredump_memory_buffer.crc32 = mcd_crc32b(coredump_memory_buffer.data,
+                                           memory_write_ctx.offset,
+                                           0xFFFFFFFF) ^ 0xFFFFFFFF;
+
+            mcd_println("Coredump saved to memory buffer:\n");
+            mcd_println("  Address: 0x%08X", (uint32_t)&coredump_memory_buffer);
+            mcd_println("  Size: %d bytes", memory_write_ctx.offset);
+            mcd_println("  CRC32: 0x%08X", coredump_memory_buffer.crc32);
+        }
+        else
+        {
+            mcd_println("ERROR: Memory buffer overflow or no data written");
+            mcd_println("=== MCoreDump Memory Storage Failed ===\n");
+            return MCD_ERROR;
+        }
+    }
+
+    mcd_println("=== MCoreDump Memory Storage Completed ===\n");
+
+    return MCD_OK;
+}
+
+/**
+ * @brief Generate coredump with specified output mode
+ *
+ * This is the main entry point for generating coredumps in MCoreDump system.
+ * It supports multiple output modes to accommodate different debugging scenarios:
+ * 
+ * - MCD_OUTPUT_MEMORY: Saves coredump to static memory buffer (persistent across resets)
+ * - MCD_OUTPUT_SERIAL: Outputs coredump data via serial port in hex format
+ * - MCD_OUTPUT_FILESYSTEM: Saves coredump to filesystem as ELF file (if filesystem support is enabled)
+ *
+ * The function is designed to be called from exception handlers, assert hooks,
+ * or user applications when fault analysis is needed.
+ *
+ * @param output_mode Output destination for coredump data:
+ *                    - MCD_OUTPUT_MEMORY: Store in memory buffer (recommended for fault handlers)
+ *                    - MCD_OUTPUT_SERIAL: Output via serial port (for immediate analysis)
+ *                    - MCD_OUTPUT_FILESYSTEM: Save to file (requires filesystem support)
+ *
+ * @return int Status code:
+ *             - MCD_OK: Coredump generated successfully
+ *             - MCD_ERROR: Failed to generate coredump (memory overflow, filesystem error, etc.)
+ *
+ * @note This function calls mcd_faultdump_ex() internally, which contains the actual implementation.
+ *       The memory buffer mode is particularly useful for hard fault handlers as the data
+ *       persists across system resets when power is maintained.
+ *
+ * @warning When called from interrupt context (e.g., hard fault handler), avoid using
+ *          filesystem mode as it may involve complex I/O operations.
+ *
+ * @see mcd_faultdump_ex() for detailed implementation
+ * @see mcd_check_memory_coredump() to check for existing coredumps in memory
+ * @see mcd_dump_filesystem() to save memory coredump to filesystem
+ */
+int mcd_faultdump(mcd_output_mode_t output_mode)
+{
+    /* Default to memory storage mode for exception handling */
+    return mcd_faultdump_ex(output_mode);
+}
+
+/**
+ * @brief Print coredump from memory buffer via serial output
+ *
+ * This function reads coredump data from memory buffer and prints it via serial port
+ *
+ * @return int MCD_OK on success, error code on failure
+ */
+static int mcd_dump_memory(void)
+{
+    if (!mcd_check_memory_coredump())
+    {
+        mcd_print("No valid coredump found in memory buffer.\n");
+        return MCD_ERROR;
+    }
+
+    /* Verify CRC32 */
+    uint32_t calculated_crc = mcd_crc32b(coredump_memory_buffer.data,
+                                         coredump_memory_buffer.data_size,
+                                         0xFFFFFFFF) ^ 0xFFFFFFFF;
+
+    if (calculated_crc != coredump_memory_buffer.crc32)
+    {
+        mcd_print("ERROR: Coredump data corruption detected (CRC mismatch)!\n");
+        mcd_print("Expected: 0x%08X, Calculated: 0x%08X\n",
+                   coredump_memory_buffer.crc32, calculated_crc);
+        return MCD_ERROR;
+    }
+
+    mcd_print("\n=== MCoreDump Memory Data Serial Output ===\n");
+    mcd_print("Coredump found in memory buffer:\n");
+    mcd_print("  Address: 0x%08X\n", (uint32_t)&coredump_memory_buffer);
+    mcd_print("  Size: %d bytes\n", coredump_memory_buffer.data_size);
+    mcd_print("  CRC32: 0x%08X\n", coredump_memory_buffer.crc32);
+    mcd_print("\n");
+
+    /* Calculate and display CRC32 for serial output */
+    uint32_t serial_crc = 0xFFFFFFFF;
+    uint32_t byte_count = 0;
+
+    mcd_print("coredump start : {\n");
+
+    /* Print coredump data in hex format */
+    for (uint32_t i = 0; i < coredump_memory_buffer.data_size; i++)
+    {
+        uint8_t b = coredump_memory_buffer.data[i];
+        serial_crc = mcd_crc32b(&b, 1, serial_crc) ^ 0xFFFFFFFF;
+        mcd_print("%02x", b);
+        byte_count++;
+    }
+
+    mcd_print("\n} coredump end\n");
+
+    serial_crc = ~serial_crc;
+    mcd_print("crc32 : %08x\n", serial_crc);
+    mcd_print("bytes : %d\n", byte_count);
+    mcd_print("=== MCoreDump Memory Data Serial Output Completed ===\n\n");
+
+    return MCD_OK;
+}
+MCD_CMD_EXPORT(mcd_dump_memory, Print memory coredump via serial);