/* * Copyright (c) 2006-2019, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * * Change Logs: * Date Author Notes * 2017-07-24 Tanek the first version * 2018-11-12 Ernest Chen modify copyright */ #include #include #include #include "usart.h" #include "main.h" #define _SCB_BASE (0xE000E010UL) #define _SYSTICK_CTRL (*(rt_uint32_t *)(_SCB_BASE + 0x0)) #define _SYSTICK_LOAD (*(rt_uint32_t *)(_SCB_BASE + 0x4)) #define _SYSTICK_VAL (*(rt_uint32_t *)(_SCB_BASE + 0x8)) #define _SYSTICK_CALIB (*(rt_uint32_t *)(_SCB_BASE + 0xC)) #define _SYSTICK_PRI (*(rt_uint8_t *)(0xE000ED23UL)) // Updates the variable SystemCoreClock and must be called // whenever the core clock is changed during program execution. extern void SystemCoreClockUpdate(void); void SysInit(void); // Holds the system core clock, which is the system clock // frequency supplied to the SysTick timer and the processor // core clock. extern uint32_t SystemCoreClock; static uint32_t _SysTick_Config(rt_uint32_t ticks) { if ((ticks - 1) > 0xFFFFFF) { return 1; } _SYSTICK_LOAD = ticks - 1; _SYSTICK_PRI = 0xFF; _SYSTICK_VAL = 0; _SYSTICK_CTRL = 0x07; return 0; } #if defined(RT_USING_USER_MAIN) && defined(RT_USING_HEAP) #define RT_HEAP_SIZE 2048 static uint32_t rt_heap[RT_HEAP_SIZE]; // heap default size: 4K(1024 * 4) RT_WEAK void *rt_heap_begin_get(void) { return rt_heap; } RT_WEAK void *rt_heap_end_get(void) { return rt_heap + RT_HEAP_SIZE; } #endif /** * This function will initial your board. */ void rt_hw_board_init() { /* System Clock Update */ SystemCoreClockUpdate(); /* System Tick Configuration */ _SysTick_Config(SystemCoreClock / RT_TICK_PER_SECOND); SysInit(); /* Call components board initial (use INIT_BOARD_EXPORT()) */ #ifdef RT_USING_COMPONENTS_INIT rt_components_board_init(); #endif #if defined(RT_USING_USER_MAIN) && defined(RT_USING_HEAP) rt_system_heap_init(rt_heap_begin_get(), rt_heap_end_get()); #endif } void SysInit(void) { HAL_Init(); extern void SystemClock_Config(void); SystemClock_Config(); extern void MX_GPIO_Init(void); MX_GPIO_Init(); //MX_I2C1_Init(); MX_USART1_UART_Init(); } #if !TRICE_OFF // ms32 is a 32-bit millisecond counter, counting circular in steps of 1 every ms. uint32_t ms32 = 0; #endif int main(void) { #if !TRICE_OFF TriceInit(); // This so early, to allow trice logs inside interrupts from the beginning. Only needed for RTT. TriceHeadLine(" ????????????-F030R8 "); #endif //int i = 1; //int q = 58; //int d = i + q; rt_kprintf("%s\n", __func__); //test_softbreakpoint(); #if !TRICE_OFF SysTick->CTRL |= SysTick_CTRL_TICKINT_Msk; // enable SysTick interrupt LogTriceConfiguration(); SomeExampleTrices(3); #endif /* USER CODE END 2 */ /* Infinite loop */ /* USER CODE BEGIN WHILE */ while (1) { #if !TRICE_OFF static uint32_t lastMs = 0; if( lastMs != ms32 ){ // each ms lastMs = ms32; #if TRICE_DIAGNOSTICS == 1 static uint32_t msDiag = 0; msDiag++; if(msDiag >= 3000 ){ msDiag = 0; TriceLogDiagnosticData(); } #endif static uint32_t msCheck = 0; msCheck++; if(msCheck >= 1000 ){ msCheck = 0; SomeExampleTrices(5); } #if (TRICE_BUFFER == TRICE_RING_BUFFER) || (TRICE_BUFFER == TRICE_DOUBLE_BUFFER) static uint32_t msTransfer = 0; msTransfer++; if(msTransfer >= 100 ){ msTransfer = 0; // Serve deferred trice transfer every few ms or if TRICE_BUFFER is getting filled. With an RTOS put this in a separate task. // In TRICE_RING_BUFFER && TRICE_SINGLE_PACK_MODE TriceTransfer can transmit only 1 Trice per call, so call it every 1ms then. // In TRICE_DOUBLE_BUFFER TriceTransfer transmits one half buffer. TriceTransfer(); // serve deferred output } #if TRICE_RING_BUFFER_OVERFLOW_WATCH == 1 WatchRingBufferMargins(); #endif #endif // #if ( TRICE_BUFFER == TRICE_RING_BUFFER) || ( TRICE_BUFFER == TRICE_DOUBLE_BUFFER) } /* USER CODE END WHILE */ /* USER CODE BEGIN 3 */ #endif // #if !TRICE_OFF } return 0; } void SysTick_Handler(void) { #if !TRICE_OFF ms32++; #endif /* enter interrupt */ rt_interrupt_enter(); rt_tick_increase(); /* leave interrupt */ rt_interrupt_leave(); }