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+#ifndef __UCMSIS_H__
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+#define __UCMSIS_H__
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+
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+#include <stdint.h>
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+
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+#ifdef __cplusplus
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+extern "C" {
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+#endif
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+
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+#define __I volatile const /*!< Defines 'read only' permissions */
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+#define __O volatile /*!< Defines 'write only' permissions */
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+#define __IO volatile /*!< Defines 'read / write' permissions */
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+
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+/* following defines should be used for structure members */
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+#define __IM volatile const /*! Defines 'read only' structure member permissions */
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+#define __OM volatile /*! Defines 'write only' structure member permissions */
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+#define __IOM volatile /*! Defines 'read / write' structure member permissions */
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+
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+#define __NVIC_PRIO_BITS 8U
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+
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+#define WEAK __attribute__((weak))
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+#define ALIAS(sym) __attribute__((weak, alias (sym)))
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+#define NORETURN __attribute__((noreturn))
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+#define SECTION(name) __attribute__ ((section(name)))
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+#define INLINE __attribute__((always_inline)) inline
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+#define STATIC_INLINE static INLINE
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+
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+typedef enum IRQn
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+{
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+/* ------------------- Processor Exceptions Numbers ----------------------------- */
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+ NonMaskableInt_IRQn = -14, /* 2 Non Maskable Interrupt */
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+ HardFault_IRQn = -13, /* 3 HardFault Interrupt */
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+
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+
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+
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+ SVCall_IRQn = -5, /* 11 SV Call Interrupt */
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+
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+ PendSV_IRQn = -2, /* 14 Pend SV Interrupt */
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+ SysTick_IRQn = -1, /* 15 System Tick Interrupt */
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+
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+} IRQn_Type;
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+
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+/* Memory mapping of Core Hardware */
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+#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */
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+#define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */
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+#define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */
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+#define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */
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+#define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */
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+#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */
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+#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */
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+#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */
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+
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+#define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */
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+#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */
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+#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */
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+#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */
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+#define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */
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+#define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */
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+#define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */
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+#define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE) /*!< Core Debug configuration struct */
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+
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+/**
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+ \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC).
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+ */
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+typedef struct {
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+ __IOM uint32_t ISER[8U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */
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+ uint32_t RESERVED0[24U];
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+ __IOM uint32_t ICER[8U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */
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+ uint32_t RESERVED1[24U];
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+ __IOM uint32_t ISPR[8U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */
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+ uint32_t RESERVED2[24U];
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+ __IOM uint32_t ICPR[8U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */
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+ uint32_t RESERVED3[24U];
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+ __IOM uint32_t IABR[8U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */
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+ uint32_t RESERVED4[56U];
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+ __IOM uint8_t IP[240U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */
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+ uint32_t RESERVED5[644U];
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+ __OM uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */
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+} NVIC_Type;
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+
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+#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */
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+#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */
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+
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+/**
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+ \brief Structure type to access the System Control Block (SCB).
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+ */
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+typedef struct {
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+ __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */
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+ __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */
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+ __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */
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+ __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */
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+ __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */
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+ __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */
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+ __IOM uint8_t SHP[12U]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */
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+ __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */
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+ __IOM uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */
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+ __IOM uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */
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+ __IOM uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */
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+ __IOM uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */
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+ __IOM uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */
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+ __IOM uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */
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+ __IM uint32_t PFR[2U]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */
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+ __IM uint32_t DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */
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+ __IM uint32_t ADR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */
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+ __IM uint32_t MMFR[4U]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */
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+ __IM uint32_t ISAR[5U]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */
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+ uint32_t RESERVED0[5U];
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+ __IOM uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */
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+} SCB_Type;
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+
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+/* SCB System Handler Control and State Register Definitions */
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+#define SCB_SHCSR_USGFAULTENA_Pos 18U /*!< SCB SHCSR: USGFAULTENA Position */
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+#define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */
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+
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+#define SCB_SHCSR_BUSFAULTENA_Pos 17U /*!< SCB SHCSR: BUSFAULTENA Position */
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+#define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */
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+
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+#define SCB_SHCSR_MEMFAULTENA_Pos 16U /*!< SCB SHCSR: MEMFAULTENA Position */
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+#define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */
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+
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+#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */
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+#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */
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+
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+#define SCB_SHCSR_BUSFAULTPENDED_Pos 14U /*!< SCB SHCSR: BUSFAULTPENDED Position */
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+#define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */
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+
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+#define SCB_SHCSR_MEMFAULTPENDED_Pos 13U /*!< SCB SHCSR: MEMFAULTPENDED Position */
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+#define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */
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+
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+#define SCB_SHCSR_USGFAULTPENDED_Pos 12U /*!< SCB SHCSR: USGFAULTPENDED Position */
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+#define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */
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+
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+#define SCB_SHCSR_SYSTICKACT_Pos 11U /*!< SCB SHCSR: SYSTICKACT Position */
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+#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */
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+
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+#define SCB_SHCSR_PENDSVACT_Pos 10U /*!< SCB SHCSR: PENDSVACT Position */
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+#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */
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+
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+#define SCB_SHCSR_MONITORACT_Pos 8U /*!< SCB SHCSR: MONITORACT Position */
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+#define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */
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+
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+#define SCB_SHCSR_SVCALLACT_Pos 7U /*!< SCB SHCSR: SVCALLACT Position */
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+#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */
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+
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+#define SCB_SHCSR_USGFAULTACT_Pos 3U /*!< SCB SHCSR: USGFAULTACT Position */
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+#define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */
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+
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+#define SCB_SHCSR_BUSFAULTACT_Pos 1U /*!< SCB SHCSR: BUSFAULTACT Position */
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+#define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */
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+
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+#define SCB_SHCSR_MEMFAULTACT_Pos 0U /*!< SCB SHCSR: MEMFAULTACT Position */
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+#define SCB_SHCSR_MEMFAULTACT_Msk (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/) /*!< SCB SHCSR: MEMFAULTACT Mask */
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+
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+
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+/**
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+ \brief Structure type to access the Data Watchpoint and Trace Register (DWT).
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+ */
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+typedef struct {
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+ __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */
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+ __IOM uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */
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+ __IOM uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */
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+ __IOM uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */
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+ __IOM uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */
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+ __IOM uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */
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+ __IOM uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */
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+ __IM uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */
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+ __IOM uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */
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+ __IOM uint32_t MASK0; /*!< Offset: 0x024 (R/W) Mask Register 0 */
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+ __IOM uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */
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+ uint32_t RESERVED0[1U];
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+ __IOM uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */
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+ __IOM uint32_t MASK1; /*!< Offset: 0x034 (R/W) Mask Register 1 */
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+ __IOM uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */
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+ uint32_t RESERVED1[1U];
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+ __IOM uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */
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+ __IOM uint32_t MASK2; /*!< Offset: 0x044 (R/W) Mask Register 2 */
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+ __IOM uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */
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+ uint32_t RESERVED2[1U];
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+ __IOM uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */
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+ __IOM uint32_t MASK3; /*!< Offset: 0x054 (R/W) Mask Register 3 */
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+ __IOM uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */
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+} DWT_Type;
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+
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+/**
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+ \brief Structure type to access the Memory Protection Unit (MPU).
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+ */
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+typedef struct {
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+ __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */
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+ __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */
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+ __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */
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+ __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */
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+ __IOM uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */
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+ __IOM uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Alias 1 Region Base Address Register */
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+ __IOM uint32_t RASR_A1; /*!< Offset: 0x018 (R/W) MPU Alias 1 Region Attribute and Size Register */
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+ __IOM uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Alias 2 Region Base Address Register */
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+ __IOM uint32_t RASR_A2; /*!< Offset: 0x020 (R/W) MPU Alias 2 Region Attribute and Size Register */
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+ __IOM uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Alias 3 Region Base Address Register */
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+ __IOM uint32_t RASR_A3; /*!< Offset: 0x028 (R/W) MPU Alias 3 Region Attribute and Size Register */
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+} MPU_Type;
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+
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+/**
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+ \brief Structure type to access the Core Debug Register (CoreDebug).
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+ */
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+typedef struct {
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+ __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */
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+ __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */
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+ __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */
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+ __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */
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+} CoreDebug_Type;
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+
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+
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+STATIC_INLINE uint32_t __get_CONTROL(void)
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+{
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+ uint32_t tmp;
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+ __asm__ volatile("mrs\t%0, CONTROL\n":"=r" (tmp));
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+ return tmp;
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+}
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+
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+STATIC_INLINE void __set_CONTROL(uint32_t tmp)
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+{
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+ __asm__ volatile("msr\tCONTROL, %0\n"::"r" (tmp));
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+}
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+
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+STATIC_INLINE void __set_MSP(uint32_t tmp)
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+{
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+ __asm__ volatile("msr\tMSP, %0\n"::"r" (tmp));
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+}
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+
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|
|
229
|
+/**
|
|
|
230
|
+ \brief Set Interrupt Priority
|
|
|
231
|
+ \details Sets the priority of a device specific interrupt or a processor exception.
|
|
|
232
|
+ The interrupt number can be positive to specify a device specific interrupt,
|
|
|
233
|
+ or negative to specify a processor exception.
|
|
|
234
|
+ \param [in] IRQn Interrupt number.
|
|
|
235
|
+ \param [in] priority Priority to set.
|
|
|
236
|
+ \note The priority cannot be set for every processor exception.
|
|
|
237
|
+ */
|
|
|
238
|
+STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
|
|
|
239
|
+{
|
|
|
240
|
+ if ((int32_t)(IRQn) >= 0)
|
|
|
241
|
+ {
|
|
|
242
|
+ NVIC->IP[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
|
|
|
243
|
+ }
|
|
|
244
|
+ else
|
|
|
245
|
+ {
|
|
|
246
|
+ SCB->SHP[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
|
|
|
247
|
+ }
|
|
|
248
|
+}
|
|
|
249
|
+
|
|
|
250
|
+STATIC_INLINE void __WFI(void)
|
|
|
251
|
+{
|
|
|
252
|
+ __asm__ volatile("wfi");
|
|
|
253
|
+}
|
|
|
254
|
+
|
|
|
255
|
+STATIC_INLINE void __BKPT(uint8_t n)
|
|
|
256
|
+{
|
|
|
257
|
+ __asm__ volatile("bkpt %0" : : "i" (n & 0xFF));
|
|
|
258
|
+}
|
|
|
259
|
+
|
|
|
260
|
+STATIC_INLINE void __disable_irq(void)
|
|
|
261
|
+{
|
|
|
262
|
+ __asm__ volatile ("cpsid i" : : : "memory");
|
|
|
263
|
+}
|
|
|
264
|
+
|
|
|
265
|
+STATIC_INLINE void __enable_irq(void)
|
|
|
266
|
+{
|
|
|
267
|
+ __asm__ volatile("cpsie i" : : : "memory");
|
|
|
268
|
+}
|
|
|
269
|
+
|
|
|
270
|
+#ifdef __cplusplus
|
|
|
271
|
+}
|
|
|
272
|
+#endif
|
|
|
273
|
+
|
|
|
274
|
+#endif /* __UCMSIS_H__ */
|
