[add] elog

EWARM/stm32_broad_mini.ewp

                     <state>$PROJ_DIR$/../Middlewares/rtthread/include</state>
                     <state>$PROJ_DIR$/../Middlewares/rtthread/include/libc</state>
                     <state>$PROJ_DIR$/../Middlewares/rtthread/finsh</state>
+                    <state>$PROJ_DIR$\..\Middlewares\elog</state>
                 </option>
                 <option>
                     <name>CCStdIncCheck</name>
                 <option>
                     <name>OOCOutputFormat</name>
                     <version>3</version>
-                    <state>3</state>
+                    <state>1</state>
                 </option>
                 <option>
                     <name>OCOutputOverride</name>
-                    <state>1</state>
+                    <state>0</state>
                 </option>
                 <option>
                     <name>OOCOutputFile</name>
-                    <state>project.bin</state>
+                    <state>stm32_broad_mini.hex</state>
                 </option>
                 <option>
                     <name>OOCCommandLineProducer</name>
             <data>
                 <extensions></extensions>
                 <cmdline></cmdline>
-                <hasPrio>0</hasPrio>
+                <hasPrio>96</hasPrio>
                 <buildSequence>inputOutputBased</buildSequence>
             </data>
         </settings>
                 <name>$PROJ_DIR$\..\Middlewares\coredump\coredump_cmd.S</name>
             </file>
         </group>
+        <group>
+            <name>elog</name>
+            <file>
+                <name>$PROJ_DIR$\..\Middlewares\elog\elog.c</name>
+            </file>
+            <file>
+                <name>$PROJ_DIR$\..\Middlewares\elog\elog_test.c</name>
+            </file>
+            <configuration>
+                <name>stm32_broad_mini</name>
+                <settings>
+                    <name>ICCARM</name>
+                    <data>
+                        <version>37</version>
+                        <wantNonLocal>0</wantNonLocal>
+                        <debug>1</debug>
+                        <option>
+                            <name>CCOptimizationNoSizeConstraints</name>
+                            <state>0</state>
+                        </option>
+                        <option>
+                            <name>CCDefines</name>
+                            <state>USE_HAL_DRIVER</state>
+                            <state>STM32F103xB</state>
+                        </option>
+                        <option>
+                            <name>CCPreprocFile</name>
+                            <state>0</state>
+                        </option>
+                        <option>
+                            <name>CCPreprocComments</name>
+                            <state>0</state>
+                        </option>
+                        <option>
+                            <name>CCPreprocLine</name>
+                            <state>0</state>
+                        </option>
+                        <option>
+                            <name>CCListCFile</name>
+                            <state>0</state>
+                        </option>
+                        <option>
+                            <name>CCListCMnemonics</name>
+                            <state>0</state>
+                        </option>
+                        <option>
+                            <name>CCListCMessages</name>
+                            <state>0</state>
+                        </option>
+                        <option>
+                            <name>CCListAssFile</name>
+                            <state>0</state>
+                        </option>
+                        <option>
+                            <name>CCListAssSource</name>
+                            <state>0</state>
+                        </option>
+                        <option>
+                            <name>CCEnableRemarks</name>
+                            <state>0</state>
+                        </option>
+                        <option>
+                            <name>CCDiagSuppress</name>
+                            <state></state>
+                        </option>
+                        <option>
+                            <name>CCDiagRemark</name>
+                            <state></state>
+                        </option>
+                        <option>
+                            <name>CCDiagWarning</name>
+                            <state></state>
+                        </option>
+                        <option>
+                            <name>CCDiagError</name>
+                            <state></state>
+                        </option>
+                        <option>
+                            <name>CCObjPrefix</name>
+                            <state>1</state>
+                        </option>
+                        <option>
+                            <name>CCAllowList</name>
+                            <version>1</version>
+                            <state>00000000</state>
+                        </option>
+                        <option>
+                            <name>CCDebugInfo</name>
+                            <state>1</state>
+                        </option>
+                        <option>
+                            <name>IEndianMode</name>
+                            <state>1</state>
+                        </option>
+                        <option>
+                            <name>IProcessor</name>
+                            <state>1</state>
+                        </option>
+                        <option>
+                            <name>IExtraOptionsCheck</name>
+                            <state>0</state>
+                        </option>
+                        <option>
+                            <name>IExtraOptions</name>
+                            <state></state>
+                        </option>
+                        <option>
+                            <name>CCLangConformance</name>
+                            <state>0</state>
+                        </option>
+                        <option>
+                            <name>CCSignedPlainChar</name>
+                            <state>1</state>
+                        </option>
+                        <option>
+                            <name>CCRequirePrototypes</name>
+                            <state>0</state>
+                        </option>
+                        <option>
+                            <name>CCDiagWarnAreErr</name>
+                            <state>0</state>
+                        </option>
+                        <option>
+                            <name>CCCompilerRuntimeInfo</name>
+                            <state>0</state>
+                        </option>
+                        <option>
+                            <name>IFpuProcessor</name>
+                            <state>1</state>
+                        </option>
+                        <option>
+                            <name>OutputFile</name>
+                            <state>$FILE_BNAME$.o</state>
+                        </option>
+                        <option>
+                            <name>CCLibConfigHeader</name>
+                            <state>1</state>
+                        </option>
+                        <option>
+                            <name>PreInclude</name>
+                            <state></state>
+                        </option>
+                        <option>
+                            <name>CCIncludePath2</name>
+                            <state>$PROJ_DIR$/../Core/Inc</state>
+                            <state>$PROJ_DIR$/../Drivers/STM32F1xx_HAL_Driver/Inc/Legacy</state>
+                            <state>$PROJ_DIR$/../Drivers/STM32F1xx_HAL_Driver/Inc</state>
+                            <state>$PROJ_DIR$/../Middlewares/Third_Party/FreeRTOS/Source/include</state>
+                            <state>$PROJ_DIR$/../Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS_V2</state>
+                            <state>$PROJ_DIR$/../Middlewares/Third_Party/FreeRTOS/Source/portable/IAR/ARM_CM3</state>
+                            <state>$PROJ_DIR$/../Drivers/CMSIS/Device/ST/STM32F1xx/Include</state>
+                            <state>$PROJ_DIR$/../Drivers/CMSIS/Include</state>
+                            <state>$PROJ_DIR$/../Middlewares/segger_rtt</state>
+                            <state>$PROJ_DIR$/../Middlewares/rtthread</state>
+                            <state>$PROJ_DIR$/../Middlewares/rtthread/include</state>
+                            <state>$PROJ_DIR$/../Middlewares/rtthread/include/libc</state>
+                            <state>$PROJ_DIR$/../Middlewares/rtthread/finsh</state>
+                            <state>$PROJ_DIR$\..\Middlewares\elog</state>
+                        </option>
+                        <option>
+                            <name>CCStdIncCheck</name>
+                            <state>0</state>
+                        </option>
+                        <option>
+                            <name>CCCodeSection</name>
+                            <state>.text</state>
+                        </option>
+                        <option>
+                            <name>IProcessorMode2</name>
+                            <state>1</state>
+                        </option>
+                        <option>
+                            <name>CCOptLevel</name>
+                            <state>0</state>
+                        </option>
+                        <option>
+                            <name>CCOptStrategy</name>
+                            <version>0</version>
+                            <state>1</state>
+                        </option>
+                        <option>
+                            <name>CCOptLevelSlave</name>
+                            <state>0</state>
+                        </option>
+                        <option>
+                            <name>CCPosIndRopi</name>
+                            <state>0</state>
+                        </option>
+                        <option>
+                            <name>CCPosIndRwpi</name>
+                            <state>0</state>
+                        </option>
+                        <option>
+                            <name>CCPosIndNoDynInit</name>
+                            <state>0</state>
+                        </option>
+                        <option>
+                            <name>IccLang</name>
+                            <state>0</state>
+                        </option>
+                        <option>
+                            <name>IccCDialect</name>
+                            <state>1</state>
+                        </option>
+                        <option>
+                            <name>IccAllowVLA</name>
+                            <state>0</state>
+                        </option>
+                        <option>
+                            <name>IccStaticDestr</name>
+                            <state>1</state>
+                        </option>
+                        <option>
+                            <name>IccCppInlineSemantics</name>
+                            <state>0</state>
+                        </option>
+                        <option>
+                            <name>IccCmsis</name>
+                            <state>1</state>
+                        </option>
+                        <option>
+                            <name>IccFloatSemantics</name>
+                            <state>0</state>
+                        </option>
+                        <option>
+                            <name>CCNoLiteralPool</name>
+                            <state>0</state>
+                        </option>
+                        <option>
+                            <name>CCOptStrategySlave</name>
+                            <version>0</version>
+                            <state>1</state>
+                        </option>
+                        <option>
+                            <name>CCEncSource</name>
+                            <state>0</state>
+                        </option>
+                        <option>
+                            <name>CCEncOutput</name>
+                            <state>0</state>
+                        </option>
+                        <option>
+                            <name>CCEncOutputBom</name>
+                            <state>1</state>
+                        </option>
+                        <option>
+                            <name>CCEncInput</name>
+                            <state>0</state>
+                        </option>
+                        <option>
+                            <name>IccExceptions2</name>
+                            <state>0</state>
+                        </option>
+                        <option>
+                            <name>IccRTTI2</name>
+                            <state>0</state>
+                        </option>
+                        <option>
+                            <name>CCStackProtection</name>
+                            <state>0</state>
+                        </option>
+                    </data>
+                </settings>
+            </configuration>
+        </group>
         <group>
             <name>FreeRTOS</name>
             <excluded>

EWARM/stm32f103xb_flash.icf

 define symbol __ICFEDIT_region_ROM_end__     = 0x0801FFFF;
 define symbol __ICFEDIT_region_RAM_start__   = 0x20000000;
 define symbol __ICFEDIT_region_RAM_end__     = 0x20004FFF;
+
+define symbol __ICFEDIT_region_LOG_start__   = 0x08020000;
+define symbol __ICFEDIT_region_LOG_end__     = 0x08030000;
+
 /*-Sizes-*/
 define symbol __ICFEDIT_size_cstack__ = 0x400;
 define symbol __ICFEDIT_size_heap__ = 0x200;
 define memory mem with size = 4G;
 define region ROM_region   = mem:[from __ICFEDIT_region_ROM_start__   to __ICFEDIT_region_ROM_end__];
 define region RAM_region   = mem:[from __ICFEDIT_region_RAM_start__   to __ICFEDIT_region_RAM_end__];
+define region LOG_region   = mem:[from __ICFEDIT_region_LOG_start__   to __ICFEDIT_region_LOG_end__];
 
 define block CSTACK    with alignment = 8, size = __ICFEDIT_size_cstack__   { };
 define block HEAP      with alignment = 8, size = __ICFEDIT_size_heap__     { };
 place in ROM_region   { readonly };
 place in RAM_region   { readwrite,
                         block CSTACK, block HEAP };
+
+place in LOG_region   { readonly section elog};

Middlewares/elog/elog-cpp.h

+#ifndef __ELOG_CPP_H__
+#define __ELOG_CPP_H__
+
+#define ELOG_NARG(...) \
+         ELOG_NARG_(__VA_ARGS__, ELOG_RSEQ_N())
+#define ELOG_NARG_(...) \
+         ELOG_ARG_N(__VA_ARGS__)
+#define ELOG_ARG_N( \
+          _1, _2, _3, _4, _5, _6, _7, _8, _9,_10, \
+         _11,_12,_13,_14,_15,_16,_17,_18,_19,_20, \
+         _21,_22,_23,_24,_25,_26,_27,_28,_29,_30, \
+         _31,_32,_33,_34,_35,_36,_37,_38,_39,_40, \
+         _41,_42,_43,_44,_45,_46,_47,_48,_49,_50, \
+         _51,_52,_53,_54,_55,_56,_57,_58,_59,_60, \
+         _61,_62,_63,N,...) N
+#define ELOG_RSEQ_N() \
+         63,62,61,60,                   \
+         59,58,57,56,55,54,53,52,51,50, \
+         49,48,47,46,45,44,43,42,41,40, \
+         39,38,37,36,35,34,33,32,31,30, \
+         29,28,27,26,25,24,23,22,21,20, \
+         19,18,17,16,15,14,13,12,11,10, \
+         9,8,7,6,5,4,3,2,1,0
+
+#define FIRST_(a, ...) a
+#define SECOND_(a, b, ...) b
+
+#define FIRST(...) FIRST_(__VA_ARGS__,)
+#define SECOND(...) SECOND_(__VA_ARGS__,)
+
+#define EMPTY()
+
+#define EVAL(...) EVAL1024(__VA_ARGS__)
+#define EVAL1024(...) EVAL512(EVAL512(__VA_ARGS__))
+#define EVAL512(...) EVAL256(EVAL256(__VA_ARGS__))
+#define EVAL256(...) EVAL128(EVAL128(__VA_ARGS__))
+#define EVAL128(...) EVAL64(EVAL64(__VA_ARGS__))
+#define EVAL64(...) EVAL32(EVAL32(__VA_ARGS__))
+#define EVAL32(...) EVAL16(EVAL16(__VA_ARGS__))
+#define EVAL16(...) EVAL8(EVAL8(__VA_ARGS__))
+#define EVAL8(...) EVAL4(EVAL4(__VA_ARGS__))
+#define EVAL4(...) EVAL2(EVAL2(__VA_ARGS__))
+#define EVAL2(...) EVAL1(EVAL1(__VA_ARGS__))
+#define EVAL1(...) __VA_ARGS__
+
+#define DEFER1(m) m EMPTY()
+#define DEFER2(m) m EMPTY EMPTY()()
+
+#define IS_PROBE(...) SECOND(__VA_ARGS__, 0)
+#define PROBE() ~, 1
+
+#define CAT(a,b) a ## b
+
+#define NOT(x) IS_PROBE(CAT(_NOT_, x))
+#define _NOT_0 PROBE()
+
+#define BOOL(x) NOT(NOT(x))
+
+#define IF_ELSE(condition) _IF_ELSE(BOOL(condition))
+#define _IF_ELSE(condition) CAT(_IF_, condition)
+
+#define _IF_1(...) __VA_ARGS__ _IF_1_ELSE
+#define _IF_0(...)             _IF_0_ELSE
+
+#define _IF_1_ELSE(...)
+#define _IF_0_ELSE(...) __VA_ARGS__
+
+#define HAS_ARGS(...) BOOL(FIRST(_END_OF_ARGUMENTS_ __VA_ARGS__)())
+#define _END_OF_ARGUMENTS_() 0
+
+#define MAP(m, first, ...)           \
+  m(first)                           \
+  IF_ELSE(HAS_ARGS(__VA_ARGS__))(    \
+    DEFER2(_MAP)()(m, __VA_ARGS__)   \
+  )(                                 \
+    /* Do nothing, just terminate */ \
+  )
+#define _MAP() MAP
+
+#endif /* __ELOG_CPP_H__ */

Middlewares/elog/elog-internal.h

+#ifndef __ELOG_INTERNAL_H__
+#define __ELOG_INTERNAL_H__
+
+#include <stddef.h>
+#include <stdint.h>
+#include <limits.h>
+
+#define MSGPTR_LEN_BITS (CHAR_BIT / 2)
+#define MSGPTR_LEN_BITS_OFFSET ((sizeof(msgptr_t) * CHAR_BIT) - MSGPTR_LEN_BITS)
+#define MSGPTR_MSG_MASK ((1 << MSGPTR_LEN_BITS_OFFSET) - 1)
+#define MSGPTR_LEN_MASK ((1 << MSGPTR_LEN_BITS) - 1)
+#define MSGPTR_LEN(v) (((v) >> MSGPTR_LEN_BITS_OFFSET) & MSGPTR_LEN_MASK)
+#define MSGPTR_MSG(v) ((v) & MSGPTR_MSG_MASK)
+#define MSGPTR_MAKE(l, p) (((p) & MSGPTR_MSG_MASK) | (((l) & MSGPTR_LEN_MASK) << MSGPTR_LEN_BITS_OFFSET))
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+typedef uint32_t msgptr_t;
+typedef uint32_t msgparam_t;
+
+typedef struct {
+    msgptr_t msgid;
+    msgparam_t data[0];
+} __attribute__((__packed__)) elog_entry_t;
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __ELOG_INTERNAL_H__ */

Middlewares/elog/elog.c

+#include <elog.h>
+
+#include <string.h>
+
+elog_t *elog_init(void *arena, size_t size)
+{
+    elog_t *ptr = (elog_t *)arena;
+    ptr->buflen = size - sizeof(elog_t); // Adjust for the size of the elog_t structure
+    ptr->offset = 0;
+    return ptr;
+}
+
+int elog_put(elog_t *log, const char *const msg, int n, msgparam_t args[])
+{
+    elog_entry_t *e = (elog_entry_t *)(log->buffer + log->offset); // 计算当前可写的位置e（即log->buffer）
+    long esize = n * sizeof(msgparam_t); // 参数占用字节数
+    long newoff = log->offset + sizeof(elog_entry_t) + esize; // 计算新的偏移量，开始是elog_entry_t头 + n个msg（id和长度组成）
+
+    if (newoff < log->buflen)
+    {
+        e->msgid = MSGPTR_MAKE(n, (msgptr_t)msg); // 通过字符串地址和个数生成msgid，并写入e
+        memcpy(e->data, args, esize); // 参数列表写入e
+        log->offset = newoff;
+        return 1;
+    }
+
+    return 0;
+}
+
+void elog_flush(elog_t *log, elog_flush_func_t func, void *ctx)
+{
+    long off = 0;
+
+    while (off < log->offset) // 也可以直接发送出去上位机，在上位机端解码
+    {
+        elog_entry_t *e = ((elog_entry_t *)(log->buffer + off));
+        size_t len = MSGPTR_LEN(e->msgid) * sizeof(long);
+        size_t incr = sizeof(elog_entry_t) + len;
+        off += incr;
+        func(e, incr, ctx); // 解出一个e[id + data]
+    }
+
+    log->offset = 0;
+}

Middlewares/elog/elog.h

+#ifndef __ELOG_H__
+#define __ELOG_H__
+
+#include <stddef.h>
+
+#include "elog-cpp.h"
+#include "elog-internal.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+typedef struct {
+    ptrdiff_t buflen;
+    ptrdiff_t offset;
+    char buffer[0];
+} __attribute__((__packed__)) elog_t;
+
+#define _msgparam_cast_apply(x) ((long) (x)),
+#define msgparam_cast_apply(...) EVAL(MAP(_msgparam_cast_apply, __VA_ARGS__))
+
+#define ELOG(o, msg, ...) do { \
+    __attribute__((section("elog"))) static const char p_msg[] = msg;  \
+    IF_ELSE(HAS_ARGS(__VA_ARGS__))(    \
+        elog_put(o, p_msg, ELOG_NARG(__VA_ARGS__)/*计算出有多少个参数*/, (msgparam_t[]){ msgparam_cast_apply(__VA_ARGS__) }/*参数数组*/); \
+    )(                                 \
+        elog_put(o, p_msg, 0, (msgparam_t[]){}); \
+    ) \
+} while(0)
+
+typedef void (elog_flush_func_t)(elog_entry_t *e, int len, void *ctx);
+
+extern elog_t *elog_init(void *arena, size_t size);
+extern int elog_put(elog_t *log, const char *const msg, int n, msgparam_t args[]);
+extern elog_entry_t *elog_peek(elog_t *log);
+extern void elog_flush(elog_t *log, elog_flush_func_t func, void *ctx);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __ELOG_H__ */

Middlewares/elog/elog_test.c

+#include <elog.h>
+
+static elog_t *logger;
+static char arena[1024];
+
+static void log_to_semihost(elog_entry_t *e, int len, void *ctx)
+{
+    // 发送出去
+    uint32_t *p = (void *)e;
+    int num = len / sizeof(uint32_t);
+    rt_kprintf("num:%d\n", num);
+    rt_kprintf("len:%d\n", MSGPTR_LEN(p[0])); // 通过msg->id解出参数个数
+
+    for(int i = 0; i < num; i++)
+    {
+        if(0 == i)
+            rt_kprintf("0x%08X ", MSGPTR_MSG(p[i])); // 通过msg_id解出参数内容
+
+        rt_kprintf("%d ", p[i]);
+    }
+
+    rt_kprintf("\n\n");
+}
+
+int elog_test(void)
+{
+    logger = elog_init(arena, sizeof(arena));
+    ELOG(logger, "Hello world %d\n", 10);  // 把字符串和参数放到内存中，（通过字符串 + 长度算法生成msg_id）和会形成一条msg_id和长度
+    ELOG(logger, "test %d %d %c\n", 1, 2, 3);
+
+    elog_flush(logger, log_to_semihost, NULL);  // 将内存中的日志刷新到文件，也可以是传输到上位机。也就是之前(字符串和参数)生成的msg_id和长度
+    return 0;
+}

Middlewares/elog/ucmsis.h

+#ifndef __UCMSIS_H__
+#define __UCMSIS_H__
+
+#include <stdint.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#define     __I     volatile const       /*!< Defines 'read only' permissions */
+#define     __O     volatile             /*!< Defines 'write only' permissions */
+#define     __IO    volatile             /*!< Defines 'read / write' permissions */
+
+/* following defines should be used for structure members */
+#define     __IM     volatile const      /*! Defines 'read only' structure member permissions */
+#define     __OM     volatile            /*! Defines 'write only' structure member permissions */
+#define     __IOM    volatile            /*! Defines 'read / write' structure member permissions */
+
+#define __NVIC_PRIO_BITS          8U
+
+#define WEAK __attribute__((weak))
+#define ALIAS(sym) __attribute__((weak, alias (sym)))
+#define NORETURN __attribute__((noreturn))
+#define SECTION(name) __attribute__ ((section(name)))
+#define INLINE __attribute__((always_inline)) inline 
+#define STATIC_INLINE static INLINE
+
+typedef enum IRQn
+{
+/* -------------------  Processor Exceptions Numbers  ----------------------------- */
+  NonMaskableInt_IRQn           = -14,     /*  2 Non Maskable Interrupt */
+  HardFault_IRQn                = -13,     /*  3 HardFault Interrupt */
+
+
+
+  SVCall_IRQn                   =  -5,     /* 11 SV Call Interrupt */
+
+  PendSV_IRQn                   =  -2,     /* 14 Pend SV Interrupt */
+  SysTick_IRQn                  =  -1,     /* 15 System Tick Interrupt */
+
+} IRQn_Type;
+
+/* Memory mapping of Core Hardware */
+#define SCS_BASE            (0xE000E000UL)                            /*!< System Control Space Base Address */
+#define ITM_BASE            (0xE0000000UL)                            /*!< ITM Base Address */
+#define DWT_BASE            (0xE0001000UL)                            /*!< DWT Base Address */
+#define TPI_BASE            (0xE0040000UL)                            /*!< TPI Base Address */
+#define CoreDebug_BASE      (0xE000EDF0UL)                            /*!< Core Debug Base Address */
+#define SysTick_BASE        (SCS_BASE +  0x0010UL)                    /*!< SysTick Base Address */
+#define NVIC_BASE           (SCS_BASE +  0x0100UL)                    /*!< NVIC Base Address */
+#define SCB_BASE            (SCS_BASE +  0x0D00UL)                    /*!< System Control Block Base Address */
+
+#define SCnSCB              ((SCnSCB_Type    *)     SCS_BASE      )   /*!< System control Register not in SCB */
+#define SCB                 ((SCB_Type       *)     SCB_BASE      )   /*!< SCB configuration struct */
+#define SysTick             ((SysTick_Type   *)     SysTick_BASE  )   /*!< SysTick configuration struct */
+#define NVIC                ((NVIC_Type      *)     NVIC_BASE     )   /*!< NVIC configuration struct */
+#define ITM                 ((ITM_Type       *)     ITM_BASE      )   /*!< ITM configuration struct */
+#define DWT                 ((DWT_Type       *)     DWT_BASE      )   /*!< DWT configuration struct */
+#define TPI                 ((TPI_Type       *)     TPI_BASE      )   /*!< TPI configuration struct */
+#define CoreDebug           ((CoreDebug_Type *)     CoreDebug_BASE)   /*!< Core Debug configuration struct */
+
+/**
+  \brief  Structure type to access the Nested Vectored Interrupt Controller (NVIC).
+ */
+typedef struct {
+   __IOM uint32_t ISER[8U];               /*!< Offset: 0x000 (R/W)  Interrupt Set Enable Register */
+   uint32_t RESERVED0[24U];
+   __IOM uint32_t ICER[8U];               /*!< Offset: 0x080 (R/W)  Interrupt Clear Enable Register */
+   uint32_t RESERVED1[24U];
+   __IOM uint32_t ISPR[8U];               /*!< Offset: 0x100 (R/W)  Interrupt Set Pending Register */
+   uint32_t RESERVED2[24U];
+   __IOM uint32_t ICPR[8U];               /*!< Offset: 0x180 (R/W)  Interrupt Clear Pending Register */
+   uint32_t RESERVED3[24U];
+   __IOM uint32_t IABR[8U];               /*!< Offset: 0x200 (R/W)  Interrupt Active bit Register */
+   uint32_t RESERVED4[56U];
+   __IOM uint8_t  IP[240U];               /*!< Offset: 0x300 (R/W)  Interrupt Priority Register (8Bit wide) */
+   uint32_t RESERVED5[644U];
+   __OM  uint32_t STIR;                   /*!< Offset: 0xE00 ( /W)  Software Trigger Interrupt Register */
+}  NVIC_Type;
+
+#define SCB_ICSR_PENDSVSET_Pos             28U                                            /*!< SCB ICSR: PENDSVSET Position */
+#define SCB_ICSR_PENDSVSET_Msk             (1UL << SCB_ICSR_PENDSVSET_Pos)                /*!< SCB ICSR: PENDSVSET Mask */
+
+/**
+  \brief  Structure type to access the System Control Block (SCB).
+ */
+typedef struct {
+   __IM  uint32_t CPUID;                  /*!< Offset: 0x000 (R/ )  CPUID Base Register */
+   __IOM uint32_t ICSR;                   /*!< Offset: 0x004 (R/W)  Interrupt Control and State Register */
+   __IOM uint32_t VTOR;                   /*!< Offset: 0x008 (R/W)  Vector Table Offset Register */
+   __IOM uint32_t AIRCR;                  /*!< Offset: 0x00C (R/W)  Application Interrupt and Reset Control Register */
+   __IOM uint32_t SCR;                    /*!< Offset: 0x010 (R/W)  System Control Register */
+   __IOM uint32_t CCR;                    /*!< Offset: 0x014 (R/W)  Configuration Control Register */
+   __IOM uint8_t  SHP[12U];               /*!< Offset: 0x018 (R/W)  System Handlers Priority Registers (4-7, 8-11, 12-15) */
+   __IOM uint32_t SHCSR;                  /*!< Offset: 0x024 (R/W)  System Handler Control and State Register */
+   __IOM uint32_t CFSR;                   /*!< Offset: 0x028 (R/W)  Configurable Fault Status Register */
+   __IOM uint32_t HFSR;                   /*!< Offset: 0x02C (R/W)  HardFault Status Register */
+   __IOM uint32_t DFSR;                   /*!< Offset: 0x030 (R/W)  Debug Fault Status Register */
+   __IOM uint32_t MMFAR;                  /*!< Offset: 0x034 (R/W)  MemManage Fault Address Register */
+   __IOM uint32_t BFAR;                   /*!< Offset: 0x038 (R/W)  BusFault Address Register */
+   __IOM uint32_t AFSR;                   /*!< Offset: 0x03C (R/W)  Auxiliary Fault Status Register */
+   __IM  uint32_t PFR[2U];                /*!< Offset: 0x040 (R/ )  Processor Feature Register */
+   __IM  uint32_t DFR;                    /*!< Offset: 0x048 (R/ )  Debug Feature Register */
+   __IM  uint32_t ADR;                    /*!< Offset: 0x04C (R/ )  Auxiliary Feature Register */
+   __IM  uint32_t MMFR[4U];               /*!< Offset: 0x050 (R/ )  Memory Model Feature Register */
+   __IM  uint32_t ISAR[5U];               /*!< Offset: 0x060 (R/ )  Instruction Set Attributes Register */
+   uint32_t RESERVED0[5U];
+   __IOM uint32_t CPACR;                  /*!< Offset: 0x088 (R/W)  Coprocessor Access Control Register */
+} SCB_Type;
+
+/* SCB System Handler Control and State Register Definitions */
+#define SCB_SHCSR_USGFAULTENA_Pos          18U                                            /*!< SCB SHCSR: USGFAULTENA Position */
+#define SCB_SHCSR_USGFAULTENA_Msk          (1UL << SCB_SHCSR_USGFAULTENA_Pos)             /*!< SCB SHCSR: USGFAULTENA Mask */
+
+#define SCB_SHCSR_BUSFAULTENA_Pos          17U                                            /*!< SCB SHCSR: BUSFAULTENA Position */
+#define SCB_SHCSR_BUSFAULTENA_Msk          (1UL << SCB_SHCSR_BUSFAULTENA_Pos)             /*!< SCB SHCSR: BUSFAULTENA Mask */
+
+#define SCB_SHCSR_MEMFAULTENA_Pos          16U                                            /*!< SCB SHCSR: MEMFAULTENA Position */
+#define SCB_SHCSR_MEMFAULTENA_Msk          (1UL << SCB_SHCSR_MEMFAULTENA_Pos)             /*!< SCB SHCSR: MEMFAULTENA Mask */
+
+#define SCB_SHCSR_SVCALLPENDED_Pos         15U                                            /*!< SCB SHCSR: SVCALLPENDED Position */
+#define SCB_SHCSR_SVCALLPENDED_Msk         (1UL << SCB_SHCSR_SVCALLPENDED_Pos)            /*!< SCB SHCSR: SVCALLPENDED Mask */
+
+#define SCB_SHCSR_BUSFAULTPENDED_Pos       14U                                            /*!< SCB SHCSR: BUSFAULTPENDED Position */
+#define SCB_SHCSR_BUSFAULTPENDED_Msk       (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos)          /*!< SCB SHCSR: BUSFAULTPENDED Mask */
+
+#define SCB_SHCSR_MEMFAULTPENDED_Pos       13U                                            /*!< SCB SHCSR: MEMFAULTPENDED Position */
+#define SCB_SHCSR_MEMFAULTPENDED_Msk       (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos)          /*!< SCB SHCSR: MEMFAULTPENDED Mask */
+
+#define SCB_SHCSR_USGFAULTPENDED_Pos       12U                                            /*!< SCB SHCSR: USGFAULTPENDED Position */
+#define SCB_SHCSR_USGFAULTPENDED_Msk       (1UL << SCB_SHCSR_USGFAULTPENDED_Pos)          /*!< SCB SHCSR: USGFAULTPENDED Mask */
+
+#define SCB_SHCSR_SYSTICKACT_Pos           11U                                            /*!< SCB SHCSR: SYSTICKACT Position */
+#define SCB_SHCSR_SYSTICKACT_Msk           (1UL << SCB_SHCSR_SYSTICKACT_Pos)              /*!< SCB SHCSR: SYSTICKACT Mask */
+
+#define SCB_SHCSR_PENDSVACT_Pos            10U                                            /*!< SCB SHCSR: PENDSVACT Position */
+#define SCB_SHCSR_PENDSVACT_Msk            (1UL << SCB_SHCSR_PENDSVACT_Pos)               /*!< SCB SHCSR: PENDSVACT Mask */
+
+#define SCB_SHCSR_MONITORACT_Pos            8U                                            /*!< SCB SHCSR: MONITORACT Position */
+#define SCB_SHCSR_MONITORACT_Msk           (1UL << SCB_SHCSR_MONITORACT_Pos)              /*!< SCB SHCSR: MONITORACT Mask */
+
+#define SCB_SHCSR_SVCALLACT_Pos             7U                                            /*!< SCB SHCSR: SVCALLACT Position */
+#define SCB_SHCSR_SVCALLACT_Msk            (1UL << SCB_SHCSR_SVCALLACT_Pos)               /*!< SCB SHCSR: SVCALLACT Mask */
+
+#define SCB_SHCSR_USGFAULTACT_Pos           3U                                            /*!< SCB SHCSR: USGFAULTACT Position */
+#define SCB_SHCSR_USGFAULTACT_Msk          (1UL << SCB_SHCSR_USGFAULTACT_Pos)             /*!< SCB SHCSR: USGFAULTACT Mask */
+
+#define SCB_SHCSR_BUSFAULTACT_Pos           1U                                            /*!< SCB SHCSR: BUSFAULTACT Position */
+#define SCB_SHCSR_BUSFAULTACT_Msk          (1UL << SCB_SHCSR_BUSFAULTACT_Pos)             /*!< SCB SHCSR: BUSFAULTACT Mask */
+
+#define SCB_SHCSR_MEMFAULTACT_Pos           0U                                            /*!< SCB SHCSR: MEMFAULTACT Position */
+#define SCB_SHCSR_MEMFAULTACT_Msk          (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/)         /*!< SCB SHCSR: MEMFAULTACT Mask */
+
+
+/**
+  \brief  Structure type to access the Data Watchpoint and Trace Register (DWT).
+ */
+typedef struct {
+   __IOM uint32_t CTRL;                   /*!< Offset: 0x000 (R/W)  Control Register */
+   __IOM uint32_t CYCCNT;                 /*!< Offset: 0x004 (R/W)  Cycle Count Register */
+   __IOM uint32_t CPICNT;                 /*!< Offset: 0x008 (R/W)  CPI Count Register */
+   __IOM uint32_t EXCCNT;                 /*!< Offset: 0x00C (R/W)  Exception Overhead Count Register */
+   __IOM uint32_t SLEEPCNT;               /*!< Offset: 0x010 (R/W)  Sleep Count Register */
+   __IOM uint32_t LSUCNT;                 /*!< Offset: 0x014 (R/W)  LSU Count Register */
+   __IOM uint32_t FOLDCNT;                /*!< Offset: 0x018 (R/W)  Folded-instruction Count Register */
+   __IM  uint32_t PCSR;                   /*!< Offset: 0x01C (R/ )  Program Counter Sample Register */
+   __IOM uint32_t COMP0;                  /*!< Offset: 0x020 (R/W)  Comparator Register 0 */
+   __IOM uint32_t MASK0;                  /*!< Offset: 0x024 (R/W)  Mask Register 0 */
+   __IOM uint32_t FUNCTION0;              /*!< Offset: 0x028 (R/W)  Function Register 0 */
+   uint32_t RESERVED0[1U];
+   __IOM uint32_t COMP1;                  /*!< Offset: 0x030 (R/W)  Comparator Register 1 */
+   __IOM uint32_t MASK1;                  /*!< Offset: 0x034 (R/W)  Mask Register 1 */
+   __IOM uint32_t FUNCTION1;              /*!< Offset: 0x038 (R/W)  Function Register 1 */
+   uint32_t RESERVED1[1U];
+   __IOM uint32_t COMP2;                  /*!< Offset: 0x040 (R/W)  Comparator Register 2 */
+   __IOM uint32_t MASK2;                  /*!< Offset: 0x044 (R/W)  Mask Register 2 */
+   __IOM uint32_t FUNCTION2;              /*!< Offset: 0x048 (R/W)  Function Register 2 */
+   uint32_t RESERVED2[1U];
+   __IOM uint32_t COMP3;                  /*!< Offset: 0x050 (R/W)  Comparator Register 3 */
+   __IOM uint32_t MASK3;                  /*!< Offset: 0x054 (R/W)  Mask Register 3 */
+   __IOM uint32_t FUNCTION3;              /*!< Offset: 0x058 (R/W)  Function Register 3 */
+} DWT_Type;
+
+/**
+  \brief  Structure type to access the Memory Protection Unit (MPU).
+ */
+typedef struct {
+   __IM  uint32_t TYPE;                   /*!< Offset: 0x000 (R/ )  MPU Type Register */
+   __IOM uint32_t CTRL;                   /*!< Offset: 0x004 (R/W)  MPU Control Register */
+   __IOM uint32_t RNR;                    /*!< Offset: 0x008 (R/W)  MPU Region RNRber Register */
+   __IOM uint32_t RBAR;                   /*!< Offset: 0x00C (R/W)  MPU Region Base Address Register */
+   __IOM uint32_t RASR;                   /*!< Offset: 0x010 (R/W)  MPU Region Attribute and Size Register */
+   __IOM uint32_t RBAR_A1;                /*!< Offset: 0x014 (R/W)  MPU Alias 1 Region Base Address Register */
+   __IOM uint32_t RASR_A1;                /*!< Offset: 0x018 (R/W)  MPU Alias 1 Region Attribute and Size Register */
+   __IOM uint32_t RBAR_A2;                /*!< Offset: 0x01C (R/W)  MPU Alias 2 Region Base Address Register */
+   __IOM uint32_t RASR_A2;                /*!< Offset: 0x020 (R/W)  MPU Alias 2 Region Attribute and Size Register */
+   __IOM uint32_t RBAR_A3;                /*!< Offset: 0x024 (R/W)  MPU Alias 3 Region Base Address Register */
+   __IOM uint32_t RASR_A3;                /*!< Offset: 0x028 (R/W)  MPU Alias 3 Region Attribute and Size Register */
+} MPU_Type;
+
+/**
+  \brief  Structure type to access the Core Debug Register (CoreDebug).
+ */
+typedef struct {
+   __IOM uint32_t DHCSR;                  /*!< Offset: 0x000 (R/W)  Debug Halting Control and Status Register */
+   __OM  uint32_t DCRSR;                  /*!< Offset: 0x004 ( /W)  Debug Core Register Selector Register */
+   __IOM uint32_t DCRDR;                  /*!< Offset: 0x008 (R/W)  Debug Core Register Data Register */
+   __IOM uint32_t DEMCR;                  /*!< Offset: 0x00C (R/W)  Debug Exception and Monitor Control Register */
+} CoreDebug_Type;
+
+
+STATIC_INLINE uint32_t __get_CONTROL(void)
+{
+   uint32_t tmp;
+   __asm__ volatile("mrs\t%0, CONTROL\n":"=r" (tmp));
+   return tmp;
+}
+
+STATIC_INLINE void __set_CONTROL(uint32_t tmp)
+{
+   __asm__ volatile("msr\tCONTROL, %0\n"::"r" (tmp));
+}
+
+STATIC_INLINE void __set_MSP(uint32_t tmp)
+{
+   __asm__ volatile("msr\tMSP, %0\n"::"r" (tmp));
+}
+
+/**
+  \brief   Set Interrupt Priority
+  \details Sets the priority of a device specific interrupt or a processor exception.
+           The interrupt number can be positive to specify a device specific interrupt,
+           or negative to specify a processor exception.
+  \param [in]      IRQn  Interrupt number.
+  \param [in]  priority  Priority to set.
+  \note    The priority cannot be set for every processor exception.
+ */
+STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC->IP[((uint32_t)IRQn)]               = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
+  }
+  else
+  {
+    SCB->SHP[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
+  }
+}
+
+STATIC_INLINE void __WFI(void)
+{
+   __asm__ volatile("wfi");
+}
+
+STATIC_INLINE void __BKPT(uint8_t n)
+{
+   __asm__ volatile("bkpt %0" : : "i" (n & 0xFF));
+}
+
+STATIC_INLINE void __disable_irq(void)
+{
+  __asm__ volatile ("cpsid i" : : : "memory");
+}
+
+STATIC_INLINE void __enable_irq(void)
+{
+   __asm__ volatile("cpsie i" : : : "memory");
+}
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __UCMSIS_H__ */

Middlewares/elog/usemihosting.h

+#ifndef __USEMIHOSTING_H__
+#define __USEMIHOSTING_H__
+
+#include <string.h>
+
+typedef enum {
+    SYS_CLOSE = 0x02,
+    SYS_CLOCK = 0x10,
+    SYS_ELAPSED = 0x30,
+    SYS_ERRNO = 0x13,
+    SYS_FLEN = 0x0C,
+    SYS_GET_CMDLINE = 0x15,
+    SYS_HEAPINFO = 0x16,
+    SYS_ISERROR = 0x08,
+    SYS_ISTTY = 0x09,
+    SYS_OPEN = 0x01,
+    SYS_READ = 0x06,
+    SYS_READC = 0x07,
+    SYS_REMOVE = 0x0E,
+    SYS_RENAME = 0x0F,
+    SYS_SEEK = 0x0A,
+    SYS_SYSTEM = 0x12,
+    SYS_TICKFREQ = 0x31,
+    SYS_TIME = 0x11,
+    SYS_TMPNAM = 0x0D,
+    SYS_WRITE = 0x05,
+    SYS_WRITEC = 0x03,
+    SYS_WRITE0 = 0x04,
+} SemihostFunction_t;
+
+//              mode	0	1	2	3	4	5	6	7	8	9	10	11
+// ISO C fopen modea	r	rb	r+	r+b	w	wb	w+	w+b	a	ab	a+	a+b
+typedef enum {
+    SYS_OPEN_RO = 0,
+    SYS_OPEN_ROB = 1,
+    SYS_OPEN_RW = 2,
+    SYS_OPEN_RWB = 3,
+    SYS_OPEN_WO = 4,
+    SYS_OPEN_WOB = 5,
+    SYS_OPEN_WA = 6,
+    SYS_OPEN_WAB = 7,
+    SYS_OPEN_AC = 8,
+    SYS_OPEN_AB = 9,
+    SYS_OPEN_AR = 10,
+    SYS_OPEN_ARB = 11,
+} SemihostOpenMode_t;
+
+__attribute__((naked))
+static unsigned int call_semihosting(unsigned int func, void *params)
+{
+    (void) func;
+    (void) params;
+    __asm__ volatile("bkpt #0xAB\nbx lr");
+}
+
+static inline void write(int fd, const void *p, size_t n)
+{
+    void *params[] = {
+        (void*) fd,
+        (void*) p,
+        (void*) n,
+    };
+    call_semihosting(SYS_WRITE, params);
+}
+
+static inline int open(const char *path, int mode)
+{
+    void *params[] = {
+        (void*) path,
+        (void*) mode,
+        (void*) strlen(path)
+    };
+    return call_semihosting(SYS_OPEN, params);
+}
+
+static inline void close(int fd)
+{
+    void *params[] = { (void*) fd };
+    call_semihosting(SYS_CLOSE, params);
+}
+
+static inline void writestr(const char *s)
+{
+    void *params[] = { (void*) s };
+    call_semihosting(SYS_WRITE0, params);
+}
+
+#endif /* __USEMIHOSTING_H__ */

Middlewares/rtthread/board.c

 
 int main(void)
 {
-    int i = 1;
-    int q = 58;
-    int d = i + q;
+    extern int elog_test(void);
+    elog_test();
     //rt_kprintf("%s\n", __func__);
-    test_softbreakpoint();
     return 0;
 }